Best implementations of quaternary adders

This technology uses field-effect transistors that use a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFETs. The MOSFET-like CNTFETs having p and n types look the most promising ones. The technology has advantages and drawbacks:

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  CNTFETs have variable threshold voltages (according to the inverse function of the diameter). This is a big advantage compared to CMOS for which different masks are needed to get different threshold voltages.

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  Among advantages, high electron mobility, high current density, high tranductance can be quoted.

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  Lifetime issues, reliability issues, difficulties in mass production and production costs are quoted as disadvantages.

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  CNTFET technology is far from being a mature one. In 2019, a 16-bit RISC microprocessor has been built with 14,000 CNFET transistors [4]. While this is an advance for CNTFET technology, we may observe that the Intel 8086 CPU, which was a 16-bit microprocessor, has been launched in 1978 with 29,000 transistors, more than 40 years ago!

However, as CMOS circuits and CNTFET ones have basically the same circuit styles, CNTFETs can be used to propose a new implementation of quaternary adders and compare it with previous published proposals.

The transistor count is used to compare different implementations of quaternary adders. As comparisons are done by using the same technology and the same operators, the transistor count is significant as it is very doubtful that more transistors could lead to:

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  less interconnects

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  reduced chip area

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  reduced power dissipation

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  reduced propagation delays

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  Etc.

While binary circuits have 0 and 1 levels, quaternary circuits have four levels 0 < 1 < 2 < 3. The corresponding levels could be voltage, current or charge levels.

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  Charge levels. This approach is used in flash memories. 4-valued (MLC) flash memories store two bits per cell. 8-valued (TLC) memories store 3 bits per cell. In 2018, ADATA, Intel, Micron, and Samsung have launched some SSD products using QLD NAND-memory with 4 bits per cell. While binary flash memories have the advantage of faster write speeds, lower power consumption and higher cell endurance, M-valued flash memories provide higher data density and lower costs. But charges are not suitable for combinational circuits

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  Current levels. Current levels have been used, but are no longer suitable because of the static power dissipation. Power dissipation is the main issue in to-day integrated circuits.

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  Voltage levels. This is the only practical approach to design combinational circuits.

The first approach to get four different voltage levels is to use three power supplies: $V_{dd}/3$ , $2V_{dd}/3$ and $V_{dd}$. Fig. 1 presents a possible implementation using transmission gates. $S_{0},S_{1},S_{2},S_{3}$ true and complementary control inputs are used to transmit to the output one of the four voltage levels corresponding to 0, 1, 2 and 3. The 3 power supplies version of [3] uses the same scheme. This approach drawback is to use three voltage supplies instead of one in the binary case. The second approach uses only one power supply for levels 0 and 3 and generates levels 1 and 2 through resistor-like dividers. Fig. 2 shows a first implementation. There are four several pathes: only one should be active to get each output value. Transistors T1, T2, T5, T6 are always on (resistor behavior). The inputs of the other transistors should be fixed to get these transistors on or off.

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  Level 0 : T9 on ; T0, T3, T4, T7 and T8 off

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  Level 1 : T0 and T3 on ; T4, T7, T8 and T9 off

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  Level 2 : T4 and T7 on ; T0, T3, T8 and T9 off

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  Level 3 : T8 on ; T0, T3, T4, T7 and T9 off

Fig. 3 presents a variant of the previous one. Only one path with resistor-like transistors is used with two resistor-connected p and two resistor-connected n transistors. T6 is used to bypass T1 and T7 is used to bypass T4.

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  Level 0 : T9 on ; T0, T5, T6, T7 and T8 off

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  Level 1 : T0 and T7 on ; T5, T6, T8 and T9 off

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  Level 2 : T5 and T6 on ; T0, T7, T8 and T9 off

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  Level 3 : T8 on ; T0, T5, T6, T7 and T9 off

Both circuits are similar with 10 transistors. This approach has two drawbacks. Levels 1 and 2 generates static power dissipation. The resistors in pathes 1 and 2 increase the RC loads and degrade switching times compared to pathes 0 and 3.

The encoder circuits can be derived from the circuits presented in Fig. 1, Fig. 2 and Fig. 3. The decoder circuits are easy to implement. They correspond to Table I in which binary values are 0 and 3. NQI, IQI and PQI outputs are provided by 3 inverters having 3 different threshold levels. Fig. 4 shows the corresponding circuits presented in [1]. The situation is similar whether circuits use 3 or 1 power supplies. Appropriate threshold levels are got by defining the chiral number of each transistor used in the inverter.

The decoder circuit is presented in Fig 5. The circuitry is the same using 3 or 1 voltage levels. It is based on the inverters 1, 2 and 3 with the different threshold levels (such as the inverters presented in Fig. 4) followed by usual binary gates. The number of transistors depends on the implementation of the XOR gate. It ranges from 16 T when using 4 Nand gates down to 3 T as proposed in [5] (Fig.6). An acceptable value is 9 T, which corresponds to a conventional CMOS implementation used in [6]. This implementation doesn’t use pass transistors and has a full swing output. The overall transistor count for the decoder ranges from 28 T (most conservative implementation) down to 15T with 21 T as an acceptable value.

The binary to quaternary encoder circuits depend on the technique that is used to generate the four output values.

There are many different ways to implement binary adders. They differ on the use or not of transmission gates. It is out of the scope of this paper to present all the possible implementations. Fig. 8 presents two typical implementations of a full adder. The left part only uses Nand gates. The right part uses Xor and Nand gates. A CNTFET 8 T full adder (Fig. 9) has been presented [5]. This adder doesn’t restore levels and using it could raise issues, both for noise margins and switching times due to series of pass transistors. The transistor counts are respectively 36 T, 18 T and 8 T. The quaternary adder uses two binary adders, one encoder and one decoder circuits. Using 2-bit carry propagate adders, the overall transistor count for the 3 power supplies version is thus:

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  72 + 44 = 116 T without using pass transistors

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  36 + 31 = 67 T when using pass transistors for Xor gates

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  16 + 31 = 47 T when using pass transistors for Xor gates and the 8T binary adder (Fig. 9)

The single-supply version would use more transistors (+ 18 T).

Using quaternary interfaces and 2N-bit adders, N-digit quaternary adders can be implemented. CPAs, CLAs and CSAs implementations are discussed in section VIII.

The quaternary half adder presented in [2] uses the decoder circuits and the muxes presented in Fig. 15. The QTG circuits are used to implement the successor and predecessor functions. Transistor counts for QDEC and QMUX are both 16 T. The half adder based on QDEC and QMUX is presented in Fig.16. The transistor counts are

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  For QS, there are 4 QTGs and 2 QDECs for a total of 16 T*6 = 96 T.

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  For QCarry, there are 6 inverters, 6 transistors and 1 QTG for a total of 12 + 6 + 16 = 32 T.

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  The half adder has 128 T.

The corresponding full adder is not presented in [2]. However, the full adder can be easily derived. The half adder (Fig. 16) corresponds to C=0. To compute QSUM1 corresponding to C=1, only two more QTGs are needed. The final sum is derived from QSUM0 and QSUM1 by using two transmission gates and one inverter. A similar technique is used to compute the carry output, as shown in Fig. 18. Only one more QTG and two transmission gates are needed. The overall transistor count for the full adder is 96 + 32 + 6 + 16 + 4 = 154 T.

These adders also use MUXes, but implement the successor, second level successor and predecessor circuits as separate blocks. Basically, the half adder presented in Fig. 19 is similar to the half adder of Fig. 16. The corresponding full adder, presented in Fig. 20, also use the same approach than the full adder of Fig. 17 and Fig. 18. Two versions are presented, with one and three power supplies. The different components are

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  QMUX 4:1 is shown in Fig. 21. It has 12 T.

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  QMUX (not shown) is simplier with only 6T.

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  The successor circuit with 3 power supplies is shown in Fig. 22. It has 6 T. The second level successor predecessor circuits (not shown) have also 6 T. The transistor count for the 3 circuits is 18 T.

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  The successor circuit with 1 power supply is shown in Fig. 23. It has 13 T. The second level successor and the predecessor circuits (not shown) have respectively 12 T and 17 T. The transistor count for the 3 circuits is 42 T.

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  Inverters are needed for $\overline{NQI(B)},\overline{IQI(B)},\overline{PQI(B)}$, $\overline{NQI(S\_QHA)},\overline{IQI(S\_QHA)}$, $\overline{PQI(S\_QHA)}$.

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    3 power supplies: If the B inverters drive the different subblocks, the fan-out are respectively 10, 6 and 8. Only 3 inverters (6 T) are needed, but there could be fan-out and routing issues. If different B inverters are used for each subblocks, there are 12 inverters (24 T).

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    1 power supply: If the B inverters drives the different subblocks, the fan-out are respectively 11, 9 and 11. There are 3 inverters (6 T). With different inverters for each subblock, there are 12 inverters (24 T).

The overall transistor count is given in Table VIII. Obviously, the 3 power supplies version is more efficient than the version presented in [2]: customizing the implementation of the successor and predecessor functions reduces the transistor count versus using 4-valued MUXes. The 1-power supply version has far more transistors.

Fig. 24 presents a 4-bit carry look-ahead adder. The binary equations of the carry computation part are well-known:
$Gi=Ai.Bi$
$Pi=Ai\oplus Bi$ (or $Pi=Ai+Bi)$
$C1=G0+P0.C0$
$C2=G1+G0.P1+P0.P1.C0=G2+P1(G0+P0C0)$
$C3=G2+G1.P2+G0.P1.P2+P0.P1.P2.C0=G2+G1P2+P2P1(G0+P0C0)$
$C4=G3+G2.P3+G1.P2.P3+P1.P2.P3(G0+P0C0)$
Binary Gi and Pi functions are implemented respectively by Nand + Inverter and Nor + inverter. Both functions use 6 T. The optimal implementation of C1, C2, C3 and C4 uses a complex gate + one inverter. The transistor count for a 4-bit carry computation is given in Table IX. For quaternary adders, the binary G and P functions for any bit j are:
$G=((A=3)\wedge(B\geq 1))+((A\geq 2)\wedge(B\geq 2))+\\ \hskip 28.45274pt((B=3)\wedge(A\geq 1))$
$P=A3.B1+A2.B2+A1.B3$

According to Table VI, the equations can be reformulated as
$G=\overline{(A3+B0).(Ai+Bi).(B3+A0)}$
$P=\overline{\overline{A3.B1}.\overline{A2.B2}.\overline{A1.B3}}$
where A0 and B0 are the outputs of NQI inverters, Ai and BI are the outputs of IQI inverters, A3 and B3 are the outputs of PQI inverters and A1, A2, B1 and B2 are the outputs of the circuit shown in Fig. 10. Assuming that all these values are available, the transistor count is 12 T for G and 16 T for P. For 4 digits, the equations are similar with different implementations of Gi and Pi functions. The transistor count for a 4-digit carry computation is given in Table X.

The transistor count is better for the carry computation of quaternary adders versus binary ones. The increase cost of Gi and Pi implementation is compensated by the reduced number of logical levels.

For an 8-bit CSA, the binary carry computation is composed of two 4-bit skip computations. For 4-bit, it means P1 to P4 functions, a 4-input And gate and a multiplexer. For a 4-digit CSA, the carry computation uses the same number of functions with the only difference in the implemention of Pi. The transistor counts are given in Table XI.

Table XII summarizes the transistor count for the different quaternary adders:

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  QB adder corresponds to the binary implementation with binary to quaternary interfaces (section V). The different values correspond to the different ways to implement a binary full adder. The middle value is probably the most significant.

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  QFA [1] is the adder that was detailed in section VI.

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  QFA [2] is the adder that was detailed in section VII-A.

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  QFA [3] is the adder that was detailed in section VII-B.

With one power supply, interfacing a 2-bit adder with quaternary to binary interface is the best implementation. With 3 power supplies, there is no significant difference with the best MUX quaternary implementation. In both cases, the different quaternary adders have x2 or x3 the transistor count of a typical 2-bit binary adder.

Table XIII and Table XIV summarize the transistor count for the different implementations of 4-digit quaternary adders to be compared with a 8-bit binary adder. Within these tables,

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  First column is the adder type.

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  Second column is the quaternary adders built from a 8-bit binary adder with 4-to-2 decoders and 2-4 encoders. The three values correspond to 1) implementation without pass transistor, 2) a conventional implementation with pass transistors and 3) a debatable option where the Xor implementation could raise noise and switching issues. The second value is the most trustable one.

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  Third column in Table XIII corresponds to the straigthforward implementation according to the quaternary functions using 1 power supply.

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  Fourth column in Table XIV corresponds to quaternary adders (3 power supplies) using Muxes.

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  Fifth column corresponds to implementations with Muxes and customized successor and predecessor circuits.

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  The last column presents the transistor count for the binary implementation. While this implementation only uses one power supply, it is included to Table XIV for the comparisons.

Some significant results can be derived from Table XIII and Table XIV.

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  With only one power supply, the direct interfacing of a binary adder with 4-2 decoders and 2-4 encoders is the best implementation with the smallest transistor count.

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  With three power supplies, only the implementation proposed in [3] can compete with the interfacing of binary adders. We can notice than the transistor count for this implementation is optimistic as it implies that the minimal number of NQI, IQI and PQI inverters can be used without fan-out and connection issues. All the other implementations are outperformed by the direct interfacing of binary adders.

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  Obviously, the best quaternary adder is outperformed by the binary adder computing the same amount of information. This binary adder is included in the best quaternary adder, while the interfacing decoder and encoder circuits are a significant overhead.

Quaternary adders are specific combinational circuits. They have some drawbacks. Either they use three power supplies instead of one for binary circuits, or they exhibit static power dissipation and degraded switching times when using only one power supply. However, the main point is that the best implementation of quaternary adders consists in interfacing binary adders with 4 to 2 decoder and 2 to 4 encoder circuits. It means that there is no advantage to try to directly implement quaternary combinational functions. To summarize, the best quaternary adder with N digits is the corresponding 2N binary adder with a significant overhead: decoder and encoder circuits.