Emergent noise-aided logic through synchronization

Exploiting the richness in the behaviour of nonlinear dynamical systems for computational tasks has attracted extensive research interest. Various theoretical schemes have been proposed to realize reconfigurable devices using the rich patterns in chaotic systems and varied experimental implementations of these schemes have been been realized[1, 2, 3].

An interesting recent line of enquiry is the effect of noise in such schemes. This approach is crucial as this leads to the possibility of noise-aided computational devices that can utilize noise to facilitate computing. Logical Stochastic Resonance (LSR)[4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15], is one such scheme in which a bistable system driven by a subthreshold stream of inputs can generate responses consistent with a desired logical operation for an optimal window of noise. This again has been implemented in a wide variety of experimental systems[16, 17, 18, 19] that range from synthetic gene networks[20, 21, 22, 23, 24, 25], optical systems[26, 27] to coulomb coupled quantum dots[28]. More recent efforts have focused on using chaotic attractor hopping [29, 30] and strange non-chaos [31, 32] to yield logic gates.

The effect of coupling on such noisy bistable systems has garnered new interest [33, 34]. Coupling induced LSR [35] demonstrated that logic operations maybe obtained from the state variable of coupled bistable systems in an optimal window of noise.

In this work, we show a novel possibility that the logical output can be embedded in collective state of the coupled system, rather than in the state variable of one of the subsystems. This change leads to a rich construct, which can yield all 2-input logic operations for an optimal window of noise strength and coupling strength.

Consider coupled bistable systems with two kinds of coupling schemes defined as follows (refer Fig. 1),

and

Here, F can be any nonlinear function that yields a bistable potential. The terms $\eta_{1}$ and $\eta_{2}$ are two uncorrelated, zero mean, univariate Gaussian noises of noise strength $D$. The drive signals $I_{1}$ and $I_{2}$ are two low amplitude (subthreshold) input streams that encode the two binary inputs to the system. A constant asymmetrizing bias $b$ acts as the tether that morphs the bistable potential, leading to reconfigurability in our scheme. In the above equations, two kinds of coupling terms have been used. In Eq. 1, the coupling between the two subsystems is bidirectional and attractive in nature with coupling strength $c$. This typical diffusive kind of coupling interaction [36] tends to synchronize the subsystems i.e. in the context of bistable systems, the two subsystems are pulled to the same potential well. In Eq. 2, the coupling interaction is bidirectional and repulsive in nature. This form of coupling repels the states of the subsystems, thus tending to anti-synchronize the subsystems [34, 37, 38], i.e. for bistable systems, the subsystems are pushed to different potential wells. Thus, Equation 1 describes attractive coupling and Equation 2 describes repulsive coupling. In conjunction with the bias $b$, we demonstrate that changing between these two coupling forms offers another degree of control, that allows us to obtain all six fundamental logic operations (c.f. Table 2).

The signals $I_{1}$ and $I_{2}$ encode the stream of binary inputs to be processed by the logic gate, where without loss of generality $I_{1}$(or $I_{2}$) $<0$ corresponds to a $0$ (OFF state) and $I_{1}$(or $I_{2}$) $>0$ corresponds to a $1$ (ON state). It is important to note that, these input signals are subthreshold i.e., they cannot cause a transition between the potential wells on their own and the transitions are actively facilitated by the noise floor, reminiscent of logical stochastic resonance (LSR). The crucial differentiating factor of this scheme from all previous attempts to achieve noise-aided logic operations is that the output from the system is embedded in the collective state of the coupled system. Specifically, the synchronization state of the two subsystems embeds outputs corresponding to logical operations on the input streams. As a convention, the synchronized state (both systems in same potential well) is taken to encode $0$ and the anti-synchronized state (both systems in different potential wells) is taken to encode $1$. The binary input output relations represented by the six fundamental 2-input logic gates are detailed in Table 1. With these conventions in place, we now show that this scheme is capable of producing all the six fundamental logic operations in a robust, reliable manner over a large region of parameter space.

The scheme is first implemented in silico, by numerically simulating Eqns. 1 and 2 using the Euler-Maruyama method. For the bistable potential, we use the simple cubic function $F(x_{i})=4(x_{i}-5x_{i}^{3})$. The input signals $I_{1}$ and $I_{2}$ are taken to assume the values $-0.5$ for the binary input $0$ and $+0.5$ for binary input $1$. The timetrials of the system variables $x_{1}$ and $x_{2}$ thus obtained, are depicted in Fig. 2 for various values of noise strength $D$, coupling strength $c$ and bias $b$. In this figure, the top two panels, show the input streams $I_{1}$(blue) and $I_{2}$(orange) being fed into the two subsystems and the expected logical output(green) of these inputs for each of the six logic operations are overlaid on the timetrails as a visual aid to perceive the correct logical operation. For the six cases depicted, the timetrails of $x_{1}$ and $x_{2}$ constantly alternate between the synchronized and anti-synchronized states modulated by the input streams. As defined earlier, the logical output is considered $0$ when the two state variables are in the same potential wells (synchronized) and $1$ when the state variables are in the opposite potential wells (anti-synchronized). From Fig. 2 it is apparent that robust logic operations are obtained at specific parameter values and coupling forms, for all six types of logic gates.

Next we construct a proof-of-principle electronic implementation of the scheme. Two piecewise-linear bistable circuits were built, using simple passive components and two operational amplifiers(op-amps) as depicted in Fig. 3. The detailed description and characterization of the bistable circuit used can be found in reference [39]. The two bistable units were coupled attractively via a resistor as shown in Fig. 3a or repulsively via inverting amplifiers as shown in Fig. 3b. The inputs and bias to the bistable system are fed through the inverting input of the op-amps, hence the signals and biases were inverted to stay consistent with the scheme description and the numerical exploration. The non-dimensionalized form of the coupled equation governing the circuits in Fig. 3a (attractively coupled circuit) and Fig. 3b (repulsively coupled circuit) assumes the form described in Eq.1 and Eq.2 respectively. Where, F of bistable unit is given by the piece-wise linear function,

In Fig. 4 oscilloscope trails of $V_{1}$(yellow) and $V_{2}$(blue) obtained from the attractive circuit (left) and repulsive circuit (right) are presented. The top panel shows the input streams ($I_{1}$ and $I_{2}$) driving the coupled system while the remaining six panels clearly show robust logic response akin to the behaviour observed in Fig. 2. The expected logic output of the input streams are again overlaid(in red) as a visual aid. The synchronized segments faithfully map to the output $0$ while the anti-synchronized segments map to $1$ for all six logical operations.

The attractive and repulsive coupling schemes yield three logic gates each. The attractive scheme yields AND, NOR and XNOR gates, while the repulsive scheme yields NAND, OR and XOR gate. Notice that the two schemes yield complementary logic operations for the same set of parameter values, suggesting that these two coupling schemes are symmetric counterparts of one another. Within a specific coupling form, the value of the constant bias $b$ (positive, negative or zero) determines the logical operation obtained from the system. The bias ranges and the coupling forms where each of the six logic operations occur, are detailed in Table 2.

Robust operation of the scheme, has been demonstrated both using simulation and experiment for a stream of inputs, with specific values of system parameters. The performance of this system is now quantified with a large number of input sets over a significant section of the parameter space. To do this, the system is subject to a large number of ($I_{1}-I_{2}$) sets, divided into runs where each run consists of a permutation of the four input sets $(0,0)$, $(0,1)$, $(1,0)$, $(1,1)$ and the response of the systems to these inputs are recorded. A run is considered successful, only if the system produced the correct logical output (corresponding to each truth table c.f. 1) throughout the run-time of each signal pulse for all four input sets. The probability of obtaining a specific logic operation $P(logic)$ is then defined as the ratio of successful runs to the total number of runs sampled. A small transient time amounting to one tenth the duration of each input pulse is allowed for the system to respond to each new input set. The $P(logic)$ corresponding to specific logic operations are denoted as P(AND), P(XOR), etc. This measure is then obtained for a large range of parameter values to ascertain the prevalence of reliable logic operations.

In Fig. 5, numerically obtained probabilities of obtaining different logic gates are plotted for a range of noise strengths $D$ and coupling strengths $c$. In these simulations the $P(logic)$ was determined by subjecting the system to 100 runs as described earlier, for each combination of parameter values. Reliable logic operations were seen to occur in large sections of parameter space where the $P(logic)$ value tends to $1$ (bright yellow regions in Fig. 5). The probability plots were made for each of the six logic operations at the corresponding coupling scheme and bias $b$ values mentioned in Table 2. Thus, we see that for a window of optimal noise strengths and coupling strengths, all logic operations can be obtained. The coupling form and bias $b$ act as the control to morph the coupled system from one logic operation to the other. Note that contrary to coupling induced LSR[35], where robust logic occurs for all values above a critical coupling strength, we find an optimal range of coupling strengths yield reliable logic operations.

To further strengthen this assertion, we also obtain the same stringent measure of reliable operations $P(logic)$, from the experimental implementation of the scheme. This was made possible by interfacing and voltage data analysis through the high speed DAQ. The experimental circuits were driven by an input stream containing 100 runs with a permutation of the four input sets $(0,0)$, $(0,1)$, $(1,0)$, $(1,1)$ in every run. Again, $P(logic)$ is obtained from the ratio of successful runs to total number of runs sampled. The inputs were fed into the system at 10Hz (10 binary inputs per second) and again one tenth of that pulse width was allowed as transient and was not included in the computation of $P(logic)$. Experimentally, two values of coupling resistances were studied, $R=300~{}\Omega$ and $R=10~{}K\Omega$. The distribution of $P(logic)$ thus obtained for all the six logic gates are shown in Fig. 6. A clear maximization of reliable logic operations, occurs for a broad window of noise strength $D$ for all the logic operations. Surprisingly, contrary to the numerical exploration experimentally we find a more robust and broad region of XOR and XNOR operations. Note that the XOR/XNOR operations were the hardest to implement in the past, and their realization necessitated the use of more complicated triple well potentials [40], where specific output definitions were assigned for each logic operation. Here, the multiple gates emerge from the collective dynamics of the coupled system and the binary outputs are inferred from their synchronization state.

A novel scheme to make reconfigurable noise aided logic gates, based on synchronization of coupled nonlinear systems, was introduced. This scheme was implemented both through numerical simulations and electronic experiments. The robustness of the logical operations and the reconfigurability of the scheme was elucidated for both attractive and repulsive coupling. A quantitative measure of performance was used to characterize the region in parameter space of coupling strength and noise strength where reliable logic operations can be obtained. This was done both in simulations and in circuit experiments through live collection and processing of high throughput voltage data. Importantly, all six fundamental logic operations were reliably obtained, using a bias and the coupling form to morph between the logic functionalities. So our results suggest the potential of exploiting synchronization, arising from the interplay of noise and the nature of coupling, to implement flexible logic gates in the presence of a noise floor.