High-Bandwidth, Low-Computational Approach: Estimator-Based Control for Hybrid Flying Capacitor Multilevel Converters Using Multi-Cost Gradient Descent and State Feedforward

The hybrid FCML’s multivariable control objectives, including the flying capacitor voltages, output voltage, and inductor current, present a challenging control problem due to the multiple control inputs and outputs in this multi-inpue multi-output (MIMO) system. The design problem can be simplified by organizing controllers in a cascaded loop, as shown in Fig. 3. This setup allows each control layer to be designed independently:

• •

  The inner loop controller is assumed to have infinite bandwidth when designing the outer loop controller.

• •

  The outer loop estimator/sampler is assumed to have infinite bandwidth when designing the inner loop controller.

These assumptions are applied to FCML controllers and estimator as follows:

Here, the settling time, $\tau$, is the inverse of the control bandwidth, $\omega$. The subscripts $CC$, $VC$, $VB$, and $VE$ represent the current controller, voltage controller, active balancing controller, and flying capacitor voltage estimator, respectively.

Meanwhile, in digital control systems, delays can arise that are not typically present in continuous-time systems. Control variables, such as inductor current, are sampled using a zero-order hold, and the pole voltage reference generated by the current controller introduces specific delays:

• •

  The reference is updated as a PWM comparator input in the next sampling period, introducing a one-sample delay.

• •

  The average PWM voltage is applied halfway through the sampling period, resulting in a cumulative delay of 0.5 sampling periods, which directly impacts the controller’s stability margin.

Therefore, the PWM pole voltage is effectively delayed by 1.5$\tau_{s}$. To mitigate instability caused by these delays, the sampling period should be much shorter than the controller’s settling time, as indicated by:

where ${\tau}_{s}$ is the sampling period. According to the time-scale separation principle in (2), (3), and (4), each controller’s bandwidth can be maximized while time-scale separation principle minimizes stability impacts between control layers while ensuring a fast response.

To reduce the impact of switching ripple in sampled inductor current, the sampling frequency is typically synchronized with the PWM carrier, with sampling taking place at the peak or valley of the PWM carrier [26]. For phase-shifted PWM (PSPWM), the sampling period (${\tau}_{s}$) is therefore aligned with the PWM carrier period (${\tau}_{sw}$) as follows:

where $m_{s}$ is a positive integer.

Since the effective switching frequency of the FCML converter with PSPWM typically reaches several hundred kHz [27], and given the computational requirements per control cycle, the sampling and control frequencies are generally set between 10 and 40 kHz to ensure sufficient real-time processing capacity. The choice of sampling frequency is based on the computational load and the capabilities of the digital signal processor (DSP) in use; here, the TMS3202837xX CPU from Texas Instruments is considered.

The following subsections outline the design of the controller and estimator for the FCML, with each controller following a generalized PIR (Proportional-Integral-Resonant) framework shown in Fig. 4. Each controller can be modified according to specific control objectives.

In this framework, $x$ and $y$ represent the input and output variables of the controller, respectively. Here, $x^{*}$, $\tilde{x}$, and $x_{aw}$ stand for the input reference, input error, and anti-windup input, respectively, while $y^{*}$, $y_{pir}$, $y_{ff}$, $y_{ad}$, and $y^{*}_{sat}$ denote the output reference, PIR controller output, feedforward input, active damping input, and the final output reference. Control switches $\gamma_{aw}$, $\gamma_{r}$, $\gamma_{i}$, and $\gamma_{en}$ are used to enabling functions for anti-windup, resonant integrators, integrators, and the overall controller, respectively. For reference values, a superscript * is used throughout this paper. The following TABLE I summarizes this information for clarity.

The controller gain is set to match the desired bandwidth by appropriately placing poles in the Laplace domain, based on the closed-loop transfer function of the plant and controller. Detailed formula-based gain settings for each controller are skipped in this paper.

The control problem and the plant dynamic equation are:

, respectively. Here, $i_{L}$, $C_{out}$, and $R_{load}$ denotes the inductor current, output capacitance, and load resistance, respectively.

For DC/DC operation of the FCML [20], an integrator in the controller is essential to eliminate steady-state error when using a DC reference. However, during scenarios such as initial charging or sudden load changes, large voltage errors may push the voltage controller’s output beyond the current limit, which clamps the current reference and reduces the voltage controller’s effective bandwidth.

Additionally, during current reference clamping, error accumulation in the integrator can lead to overshoot or undershoot in the output voltage, even after reaching the target voltage $v^{*}_{out}$. This, referred to as ‘integrator wind-up,’ can occur in any controller with an integrator and output clamping. To address this, an anti-windup mechanism can be applied to mitigate the the error accumulation. With these considerations, the voltage controller is designed as follows:

where $\operatorname{sgn}$ represents the sign function, and $i_{L,\max}$ is the maximum available inductor current.

For AC/DC boost operation (e.g., power factor correction), the only difference from DC/DC is the presence of an AC power flow component at twice the line frequency [6]. To control the DC output voltage, this AC power component can be filtered out by $F(s)$ ($F(0)=1$, $F(j2n\omega_{g})=0$), or current controller can have multi-resonant controller ($\gamma_{r}=1$) to eliminate the odd harmonic current component from voltage controller.

For unity power factor operation, the current reference is multiplied by a unit sinusoidal waveform whose phase matches the grid phase using a phase-locked-loop (PLL). The output of controller with current limitation is as follows:

where $\hat{\theta}_{g}$ is estimated grid phase from the PLL. $\omega_{g}$ denotes nominal angular frequency of grid.

For AC/DC buck operation with an output inductor [13, 14], two key points are noted:

• •

  Power transfer between the grid and the FCML only occurs when the grid voltage magnitude surpasses the output voltage (e.g., 48 V in data center applications)

• •

  The input voltage (grid voltage folded by rectifier) varies at twice the line frequency.

This results in both current and voltage containing DC and AC components with its harmonics. To manage these characteristics effectively, a proportional-resonant-integral (PIR) controller can be utilized as follows:

The controller’s output with current limitation is defined as follows:

Here, $\psi$ denotes the current reference waveform, which is synchronized with the grid voltage to ensure a high power factor. $\phi$ compensates for the effects of the input capacitor and filter on the grid current [14]. It is crucial to set $i_{L,\max}$ with consideration for any amplitude increase resulting from $\phi$.

Meanwhile, when $|v_{grid}|<v_{out}$, the FCML converter is unable to draw power from the grid. In this case, no control or estimation is needed, and all stored energy in the flying capacitors and inductors remains constant, except for the output capacitor, which is gradually discharged by the load. The controller can be disabled to prevent unnecessary operation and error accumulation in integrators as follows:

The control problem for flying capacitor voltages is defined as follows:

where ${{\mathbf{v}}_{\mathbf{c}}}={{\left[\begin{matrix}{{v}_{c,1}}&{{v}_{c,2}}&\ldots&{{v}_{c,N-2}}\\ \end{matrix}\right]}^{\mathbf{T}}}$ denotes the flying capacitor voltage vector, $\mathbf{k}=[1\;2\;\ldots\;N-2]^{\mathbf{T}}$ is the scaling vector, and $\mathbf{\Delta d}=[\Delta d_{1}\;\Delta d_{2}\;\ldots\;\Delta d_{N-2}]^{\mathbf{T}}$ represents the duty cycle differences. Each element $\Delta d_{k}=d_{k+1}-d_{k}$ for $k\in\left[1,N-2\right]$, where $d_{k}$ is the PWM duty cycle of the $k$-th switch shown in Fig. 2. Here, the hat symbol ($\hat{x}$) denotes an estimated value.

All controllers adhere to the principle of time-scale separation; therefore by enforcing $\mathbf{v_{c}}\approx\mathbf{\hat{v}_{c}}$, the following plant equation for flying capacitor voltages can be considered:

where $\Delta\mathbf{S}=\left[\begin{matrix}\Delta{{S}_{1}}&\Delta{{S}_{2}}&\cdots&\Delta{{S}_{N-2}}\\ \end{matrix}\right]^{\mathbf{T}}$, and $\Delta{{S}_{k}}={{S}_{k+1}}-{{S}_{k}}$ for $k\in\left[1,N-2\right]$. The averaged plant equation over a sampling period ($\tau_{s}$) becomes:

This indicates that changes in flying capacitor voltages ($\mathbf{v_{c}}$) are influenced by both the duty cycle difference ($\mathbf{\Delta d}$) and the inductor current ($i_{L}$). Since $i_{L}$ is controlled by the output voltage controller, $\mathbf{\Delta d}$ remains the only variable available for controlling $\mathbf{v_{c}}$. Therefore, the active balancing controller can be implemented simply with a proportional controller as follows:

It becomes necessary to limit $\mathbf{\Delta d}$ with $\mathbf{{\Delta}d_{\max}}$ when low inductor current results in a large $\mathbf{\Delta d}$. Excessive $\mathbf{\Delta d}$ can lead to a loss of inductor current control. $\mathbf{{\Delta}d_{\max}}$ prevents duty cycle saturation, thereby preserving stability in the current controller.

For AC/DC buck operation, which requires high-bandwidth active voltage balancing, maintaining accurate voltage balance becomes increasingly critical as the input voltage ($v_{in}$) rises, helping to minimize stress on switching devices.

In contrast, at lower $v_{in}$ levels, there is more tolerance for voltage imbalance, allowing minor control inaccuracies without major impact. Additionally, when $v_{in}$ is low, $d_{N-1}$ operates near its maximum duty cycle of 1, so $\mathbf{\Delta d}$ can potentially cause $d_{N-1}$ to reach saturation. This occurs even though active balancing is less critical than current control under these conditions. With these considerations, the controller can be disabled as follows:

where $m>1$ provides a margin for disabling the active voltage balancing controller.

The control objective and plant equation for inductor current are defined as follows:

respectively. The time-averaged plant equation over a sampling period ($\tau_{s}$) is:

To reduce disturbances from the output voltage ($v_{out}$) and differential term of flying capacitor voltages, the following feedforward term ($y_{ff}$) is applied:

For estimator-based control, estimated flying capacitor voltages ($\mathbf{\hat{v}_{c}}$) are used in the feedforward term, replacing $\mathbf{v_{c}}$ as shown in [21]. A reduction in estimation bandwidth or an increase in estimation error may introduce disturbances, potentially degrading the current controller’s effective bandwidth. The disturbance effect on current control becomes more severe when inductor has lower inductance [23]. Therefore, a fast and accurate estimator is required for estimator-based control.

For DC/DC boost operation, an integral controller is required for eliminating the DC steady-state error of the current. The controller configuration is as follows:

For AC/DC boost operation, where the current is primarily a sinusoidal AC component, a resonant controller is preferable to achieve zero AC steady-state error:

In AC/DC buck operation for power factor correction, the inductor current $i_{L}$ may include both DC components and even harmonics of the line frequency, as noted in (12). This setup makes an integrator and a resonant integrator ideal choices for achieving unity closed-loop gain at specific frequencies. The current controller configuration for this case is:

For all cases, parameter variations, such as changes in inductor resistance, can affect the actual bandwidth of the current controller. To maintain precise control of the bandwidth, active damping is applied as follows:

Additionally, nonlinearities in the controller, such as output limits, anti-windup mechanisms, and output scaling with specific waveforms, can introduce instability or create limit cycles with harmonic generation [28]. This consideration is important for the implementation of all controllers and estimators. To prevent these nonlinear effects in the current controller, a high-gain proportional controller can be a practical alternative:

This configuration prevents wind-up issues by avoiding use of integrators in the current controller. It does not achieve unity gain at DC and exhibits lower gain as frequency increases. However, the integrator in the output voltage controller compensates by ensuring zero steady-state error for output voltage control.

To accurately regulate the output current based on $y^{*}_{sat}$ from the voltage controller, the poles of the current controller should be placed for an overdamping response.

In designing a state estimator, it is essential to ensure observability. This involves evaluating the number of variables to be estimated and verifying that the given system matrix has full rank. For an $N$-level FCML converter, which has ($N-2$) flying capacitors, ($N-2$) independent equations are required to ensure a system matrix rank of ($N-2$).

Secondly, once observability is confirmed with a full-rank, the implementation method must be considered in terms of computational load and estimation performance, which has explicit trade-off. The simplest approach for estimating $\mathbf{v_{c}}$ is utilizing matrix inversion. However, as the number of levels in the FCML increases, the size of the state-space matrix grows significantly, containing at least $(N-2)^{2}$ elements.
Common matrix inversion algorithms have theoretical complexities ranging from $O(n^{2.81})$ to $O(n^{3})$ [29, 30]. For example, with $N=8$, where $n=8-2=6$, matrix inversion requires between approximately $6^{2.81}\approx 154$ and $6^{3}=216$ operations. This rapid increase in computational load imposes a significant burden on the CPU of MCU. In industry, where low-cost CPUs are widely preferred, such processing demands are undesirable, as they would require a more complex and costly processing unit. This challenge highlights the need for computationally efficient estimation methods.
In [24], a method with a theoretical complexity of $O(n)$ per sampling period was proposed to address the high computational load typically associated with matrix inversion. This real-time estimation technique offers an advantage by distributing computational complexity across multiple sampling instances rather than requiring full-rank conditions at each individual sample. As a result, it eliminates the need for matrix inversion while maintaining proper accuracy and bandwidth. Moreover, a balanced workload can be achieved by spreading calculations across control instances, making the computation easier to manage. However, the implementations of the method still rely on a high sampling rate and additional peripheral communication.
Finally, a well-designed estimator must utilize all available information to maximize the estimation performance. Fully utilizing the information improves the figure of merit for estimation, the superior balances can be found on the trade-off between the computational load and fast/accurate estimation.

In the proposed estimation method, the sampled current ($i_{L}$), duty cycle reference ($\mathbf{d^{*}}$), and flying capacitor voltage ($\mathbf{v_{c}}$) dynamics in (16) are utilized as new information. By incorporating this information, the estimation performance can be significantly enhanced, even with lower sampling and control frequency.

As shown in Fig. 5, for an odd-level FCML, $(N-1)$ different equations can be obtained during peak and valley sampling for the same duty reference under PSPWM, while for an even-level FCML, $2(N-1)$ different equations can be obtained. The proposed disjoint sampling method shown in Fig. 6 uses a sampler carrier synchronized with PSPWM carriers, operating at a frequency of $f_{s}$ which is much lower than effective switching frequency $(N-1)f_{sw}$. The number of different sampling instants ($N_{dis}$) is defined as follows:

Sampling is triggered when the sampler carrier reaches its valley, incrementing the interrupt counter. To utilize disjoing sampling, $m_{s}$ in (5) is selected based on the following conditions:

The sampling frequency setting differs between odd-level and even-level FCML converters. This is because, as illustrated in Fig. 5, the even number of PSPWM carriers for odd-level FCML may result in one carrier’s peak coinciding with another’s valley.

Meanwhile, the proposed method will utilize a lower sampling rate compared to [24], which makes the estimator’s closed-loop bandwidth and accuracy degraded. While the proposed method simplifies sampling implementation, it may not fully support high-bandwidth controllers based on time-scale separation. The reduced bandwidth due to lowered sampling frequency will be highly improved through state-feedforward, which will be introduced in the following chapter.

By integrating the closed-loop and open-loop estimators, the final update function is derived as follows:

where $\mathbf{\hat{v}_{c}}$, $\mathbf{\hat{v}_{fb}}$, and $\mathbf{\hat{v}_{ff}}$ are the estimated flying capacitor voltage, the feedback and feedforward terms of hybrid estimator, respectively. The block diagram of the hybrid estimator is depicted in Fig. 8.

The feedback term ensures convergence to actual value of the estimated values under steady-state conditions while guaranteeing stability of the estimator. The feedforward term compensates the limited dynamic response of the closed-loop estimator caused by lower sampling and control frequency by utilizing the fast dynamic of the open-loop estimation.

The hybrid estimator combines the strengths of both methods, enabling rapid tracking of flying capacitor voltage changes with open-loop estimation, while ensuring stability and convergence with closed-loop estimation. This approach allows for achieving high-bandwidth performance even with low sampling and control rates, making high-bandwidth estimator-based control feasible with low-cost MCU.

The mathematical analysis of the proposed hybrid estimator, including its stability and proper gain setting, will be addressed in detail in the following chapter.

(41) can be expressed in different way to analyze the stability in discrete-time domain as follows:

Here, stability of the estimator is determined by the system matrix’s eigenvalues. The system matrix is

Here, both $\mathbf{I}$ and $\mathbf{\Delta S\Delta S^{T}}$ are commutative and simultaneously diagonalizable, so the eigenvalues of system matrix are linear combinations of each matrix’s eigenvalues. Each non-zero row vector of $\mathbf{\Delta S\Delta S^{T}}$ is all paralleled each other and have a same magnitude with $\mathbf{\Delta S^{T}\Delta S}$ and the rank of $\mathbf{\Delta S\Delta S^{T}}$ is 1. Therefore, the eigenvalues of $\mathbf{\Delta S\Delta S^{T}}$ are 0 and $\mathbf{\Delta S^{T}\Delta S}$. As a result, the eigenvalues of system matrix are

To make sure the stability of the estimator, all eigenvalues should be in a range between -1 and 1, in other words, $|\lambda_{eig}[n]|<1$, therefore the following inequation should be met:

According to (48), feedback gain ($\alpha$) should satisfy following inequality:

which at least ensures the stability of the estimator. Fig. 9 shows the impact of $\alpha$ on the stability of the feedback estimator and the mathematical properties of closed-loop estimation.

(44) can be expressed as follows:

The feedback gain matrix in this formula is

which varies at every sampling instants. If the sampling frequency is significantly higher than the estimator’s bandwidth, the discrete-time update function in (49) can be approximated in continuous-time domain. The equivalent representation in continuous-time domain is expressed as follows:

Here, the proposed estimator contains variable proportional gain term, $\mathbf{K_{est}}$, and feedforward term. The laplace transform of (51) is as follows:

where

Then, (52) can be expressed with following forms:

Fig. 10 shows the closed-loop estimation performance according to the FCML level ($N$), feedback gain ($\alpha$), and sampling/control frequency ($f_{s}$). In Fig. 10(a), when $f_{s}$ is high at 300 kHz, the estimation error is small. However, Fig. 10(b) shows the estimation error increases significantly when $f_{s}$ is reduced to 30 kHz. This error includes both high-frequency errors at the sampling frequency and errors in the fundamental frequency (120 Hz). As shown in Fig. 10(c) the feedback gain ($\alpha$) is reduced to 0.05 compared to Fig. 10(b), leading to a lower bandwidth and significantly degraded estimation performance for the 120 Hz signal. Here, the estimation delay increases as bandwidth lowered. Conversely, the high-frequency error at the sampling frequency is decreased in Fig. 10(c) compared to Fig. 10(b) due to lowered $\alpha$. Interestingly, when the FCML level ($N$) is reduced to 4, decreasing the number of variables to estimate to 3, the estimation error is significantly lowered in Fig. 10(d) compared to the case in Fig. 10(b), even with the same feedback gain and sampling frequency. This is because a lower $N$ requires fewer $N_{dis}$ to satisfy full-rank operation, reducing the impact of the single-rank of the multi-cost matrix on estimation error.

In summary, the closed-loop estimation performance degrades significantly with lower sampling frequency and higher FCML level. While increasing $\alpha$ improves the estimation bandwidth, it also increases the high-frequency error caused by the single-rank of the multi-cost matrix at the sampling frequency level.

As shown in Fig. 11, the feedback term in the estimator acts as a low-pass filter as discussed in (56). It is important to note that Fig. 11 utilizes the diagonal transfer function, while the actual frequency response has a much lower bandwidth shown in Fig. 11. This is because, in a MIMO system, the bandwidth is determined by the lowest eigenvalue of the system matrix which cannot be shown in diagonal terms. A Bode plot of the transfer function, conservatively defined by the lowest eigenvalue, is shown in Fig. 12. It reveals that as $\alpha$ increases, the bandwidth also increases, but remains significantly lower than that of the diagonal transfer function in Fig. 11.

On the other hand, the feedforward term in (56), derived from the open-loop estimation, behaves as a high-pass filter, estimating high-frequency components and rapid variations.

If the parameter error is zero and sampled inductor current and applied duty is same with actual values in ideal case, then, following equality holds:

therefore,

which shows that the estimated value is exactly same with the actual value, without any estimation delay and estimation errors. The Bode plot of the hybrid estimator with feedforward is shown in Fig. 13. This shows the performance of the hybrid estimator with fast dynamics. However, in real world, the parameter/sampling error can occur, which generates the feedforward term has some error. Despite minor errors in feedforward term, Fig. 13 shows the the feedforward term enhances the estimator’s performance.

In summary, the proposed hybrid estimator separates estimation tasks: low-frequency components are handled by closed-loop feedback, while high-frequency dynamics are managed by an open-loop feedforward path. The feedforward’s high-pass filtering characteristic prevents integrator wind-up by rejecting DC errors and allowing only high-frequency dynamics. This design achieves high bandwidth without requiring excessively high sampling rates, simplifying implementation while maintaining strong dynamic performance. In contrast, conventional feedback-only methods act as low-pass filters and require a high feedback gain ($\alpha$) to minimize delay. The impact of feedforward errors, dependent on the choice of $\alpha$, will be discussed in the next chapter.

The proposed estimator employs an effective feedback gain matrix, $\mathbf{K_{\text{est}}}[n]$, as defined in (50), which varies with the switching states. Furthermore, the feedback matrix depends on the FCML level and the combinations of duty cycle references. Due to this variability, $\alpha$ must be configured to account for the worst-case scenarios, averaged over $N_{\text{dis}}$ sampling instants, as illustrated in Fig. 12. If the FCML level and operating conditions are constrained, the gain can be adjusted more flexibly, enabling improved performance under specific conditions.