High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND

An integer partition $\bm{\lambda}$ of a positive integer $m$, noted $\bm{\lambda}=(\lambda_{1},\lambda_{2},\ldots,\lambda_{P})\vdash m$, where $\lambda_{1}>\lambda_{2}>\ldots>\lambda_{P}$, is the breakdown of $m$ into a sum of strictly positive integers $\lambda_{i}$. If all $\lambda_{i}$ are different, the partition is called distinct. In the ORBGRAND algorithm, each $\lambda_{i}$ represents an index to be flipped, and therefore it requires distinct integer partitions only. The generated test error pattern obtained from an integer partition with $P$ elements has a Hamming weight of $P$.

Hardware generation of the integer partitions was proposed in [9]. However, their approach cannot be applied directly to our proposed ORBGRAND as the generated partitions are not distinct. In addition, their partition generation is sequential, which is not desirable for parallelized, high-throughput architectures. We noticed that when considering a specific logistic weight $LW$ convenient patterns appear. For example, for $LW=10$, the distinct integer partitions are $\bm{\lambda}=\{(10);(9,1);(8,2);(7,3);(6,4);(7,2,1);(6,3,1);(5,4,1);$ $(5,3,2);(4,3,2,1)\}$. If the listing order is followed for $P=2$ (i.e. the subset $\{(9,1);(8,2);(7,3);(6,4)\}$ ), the first integer descends while the second ascends. Similar trends can be observed for higher-order partitions such as $P=3$: the first integer descends while the second ascends as the third integer remains fixed until all iterations for the first two integers are complete. Inspired from this trend, we propose an arrangement of shift registers to come up with a way of generating integer partitions of a particular size, that is described in Section 4.

Without loss of generality, $\forall i\in[2,P]$, when an integer is partitioned into $P$ parts, and assuming that $\lambda_{i}$ are ordered, the maximum value for each $\lambda_{i}$ is bounded by

The first value of $\lambda$ can be found using $\lambda_{1}=m-\sum\limits_{j=2}^{P}\lambda_{j}$. The associated proof for (1) is omitted due to the lack of space.

The maximum logistic weight ($LW_{\text{max}}$) has a strong impact on both the maximum number of codebook membership queries (and essentially, the worst-case complexity) and the decoding performance. Fig. 1 plots the frame error rate (FER) performance for ORBGRAND decoding of 5G CRC-aided polar code (128, 105+11) [8, 10], with BPSK modulation over an AWGN channel. The SNR in dB is defined as $\text{SNR}=-10\log_{10}\sigma^{2}$. For $LW_{\text{max}}$ values of 128, 96 and 64, the maximum number of required queries are $5.33\times 10^{7}$, $3.69\times 10^{6}$, and $1.5\times 10^{5}$, respectively. When $LW_{\text{max}}$ is reduced from $128$ to $64$, a performance degradation of $0.2$ dB is observed at FER = $10^{-7}$. On the other hand, the complexity is reduced by $355\times$ as a result of this reduction. In addition to restricting the $LW_{\text{max}}$, the number of elements ($P$) in $\bm{\lambda}$ can also be limited. For example, for the considered polar code with $LW_{\text{max}}=64$, the degradation in error correction performance is negligible with $P=6$ when compared to an unlimited $P$. As a result of these simplifications, the maximum number of queries is reduced to $1.16\times 10^{5}$. In addition to reducing complexity, appropriate selection of parameters $LW_{\text{max}}$ and $P$ helps design simple hardware implementations.

In comparison with the hard decision variant of GRANDAB (AB=3), ORBGRAND results in a FER gain of at least 2 dB for FER lower than $10^{-5}$. Moreover, ORBGRAND with parameters $LW_{\text{max}}\leq 64$ and $P\leq 6$ results in a similar performance as the state-of-the-art Dynamic SC-Flip (DSCF) polar code decoder [11], which is also an iterative decoder. The number of attempts ($T_{\text{max}}$) parameter for DSCF is set to 50 and the maximum bit-flipping order $\omega$ is set to 2.

The VLSI architecture for the GRANDAB algorithm [12] is articulated around shift registers storing syndromes of 1-bit flip error patterns. Since this approach allows us to move the data very slightly to compute different syndromes, we use this approach as the baseline for the proposed architecture for ORBGRAND. The number of shift registers has a direct impact on the Hamming weight of error patterns, that can be computed in parallel. However, if too many shift registers are used, the amount of interconnections become problematic. Therefore, we decide to consider 3 shift registers corresponding to an integer partition of size 3 ($P=3$).

During ORBGRAND decoding, for each $LW$ ($\forall LW\in[3,LW_{\text{max}}]$), integer partitions are generated with size $P$ ($\forall P\in[2,P_{\text{max}}]$). We propose to generate these integer partitions in ascending order of their size. This modification does not impact the FER performance, however, it helps for a simpler hardware implementation. In our proposed architecture, $\lambda_{1}$, $\lambda_{2}$, $\lambda_{3}$ are mapped to first, second and third shift register. The third shift register is a $\lambda_{3}^{\text{max}}\times(n-k)$ bit shift register, where $\lambda_{3}^{\text{max}}$ value is given by (1). Whereas first and second shift registers have a size of $2\times(\lambda_{3}^{\text{max}}+1)\times(n-k)$ bits. Since we have $\lambda_{1}=n-\sum_{i=2}^{3}\lambda_{i}$, $\bm{s_{n-i}}$ is stored at the $i$th index of the first shift register; whereas for the second and third shift registers $\bm{s_{i}}$ is stored at the $i$th index.

An example of the content and the interconnection of the three shift registers corresponding to $LW=20$ is presented in Fig. 2. The elements of the shift register 1 and 2 are connected to arrays of $(n-k)$-wide XOR gates whereby a collection of these connections is defined as a bus. The $\lambda_{3}^{max}+1=6$ busses, each originating from a shift register, are used to feed the $(n-k)$-wide XOR gate arrays for computing the syndromes of the error patterns. The first array of XOR gates (dotted rectangle) is responsible to check for 2-bit flips error patterns by combining the syndromes of the received codewords with all the elements of the first and second register (the first bus of each shift register). Similarly, the remaining five XOR gate arrays combine the remaining buses ( the selected elements of the shift register 1 and 2) with the elements of the shift register 3 to check for 3-bit flips error patterns (dashed rectangle).

Due to the described layout of the 3 shift registers, all the error patterns corresponding to an integer partition of sizes 2 and 3 for a specific $LW$ are checked in one time-step. For generating test error patterns corresponding to integer partitions of sizes $P>3$, a controller is used in conjunction with the shift registers. The controller is able to combine $P_{\text{max}}-3$ syndromes together, noted $\bm{s}_{c}$. Hence, when $\bm{s}_{c}$ is fixed, only one time-step is required to generate all possible combinations of $\{\lambda_{1},\lambda_{2},\lambda_{3}\}$ using the shift registers with adequately chosen shifting values. Therefore, the number of time steps required to generate all integer partitions of size $P>3$ for a specific $LW$ is given by:

The proposed VLSI architecture for ORBGRAND is presented in Fig. 3. The control and clock signals are not depicted for simplicity. Any $\bm{H}$ matrix can be loaded into the H memory of size $n\times(n-k)\text{-bit}$ at any time to support different codes and rates. To achieve high throughput, a bitonic sorter [13] is considered to sort the incoming LLRs.

At the first step of decoding, a syndrome check is performed on the hard decided word $\hat{\bm{y}}$. If the syndrome is verified, decoding is assumed to be successful. Otherwise, the bitonic sorter is invoked to sort the LLR values. The bitonic sorter is pipelined to $\log_{2}(n)$ stages and hence it takes $\log_{2}(n)$ cycles to sort the LLRs values. While indices of the sorted LLR are forwarded to the multiplexers for later use by the word generator module, the sorted one bit-flip syndromes are passed to the decoder core, as depicted in Fig. 2. After the sorting operation, all the one bit-flip syndromes ($\bm{s_{i}}$,$\forall i\in[1,LW]$) are checked in one time-step. Next, error patterns are checked in the ascending logistic weight order. If any of the tested syndromes combinations verify the parity check constraint, a 2D priority encoder along with the controller module is used to forward the respective indices to the word generator module, where $P$ multiplexers are used to translate the sorted index values to their correct bit flip locations.

The proposed ORBGRAND architecture has been implemented in Verilog HDL and synthesized using the general-purpose TSMC 65 nm CMOS technology, using post-synthesis verified test vectors. Table 1 presents the synthesis results for the proposed decoder with $n=128$, code rates between $0.75$ and $1$, $LW\leq 64$, $P\leq 6$. Inputs are quantized on 5 bits, including 1 sign bit and 3 bits for the fractional part.

The ORBGRAND implementation supports a maximum frequency of $454~\text{MHz}$. Since no pipelining strategy is used for the decoder core, one clock cycle corresponds to one time-step. For $n=128$, $\numprint{4226}$ cycles are required in the worst-case (W.C.) scenario, resulting in a W.C. latency of 9.3$\mu$s. The average latency, however, is only of 2.47ns at SNR$=10$ dB (target FER of $10^{-7}$), which results in an average decoding information throughput of $42.5$ Gbps for a (128,105) 5G-NR CRC-Aided polar code. In comparison with the hard decision-based GRANDAB decoder (AB=3) [12], ORBGRAND has $7\times$ area overhead, and $13.5\%$ and $23\%$ higher W.C. and average latency. This translates into $13.3\%$ and $23.5\%$ lower W.C. and average decoding throughput, respectively. However, the FER performance of ORBGRAND, being a soft decision decoder, surpasses GRANDAB (AB=3) decoder by at least $2$ dB for target FER lower than $10^{-5}$, as shown in Fig. 1.

The proposed ORBGRAND is also compared with the state-of-the-art iterative Dynamic SC-Flip (DSCF) polar code decoder with similar performance [14], considering a quantization of 6 and 7 bits for channel and internal LLRs, respectively. In comparison with DSCF, ORBGRAND has $8\times$ area overhead, in addition to $52\%$ overhead in worst-case latency. However, proposed ORBGRAND results in $49\times$ lower average latency and higher average throughput than the DSCF at a target FER of $10^{-7}$. Moreover, the proposed ORBGRAND is code and rate compatible, while DSCF can only decode polar codes.