Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures

With the increased computational demands of machine learning (ML) workloads, in-memory computing (IMC) [1] architectures have attracted considerable attention to address the processor-memory bottleneck in conventional von Neumann architectures through executing the logic functions directly on memory via changing the internal memory circuitry. Resistive random access memory (RRAM) [2], phase-change memory (PCM) [3], magnetoresistive random-access memory (MRAM) [4], and conductive bridging random access memory (CBRAM) [5] are some of the promising technologies that have been utilized in IMC architectures to realize matrix-vector multiplication (MVM) operation in DNNs. While memristive technologies are also leveraged in digital IMC architectures [6, 7] to realize logic functions such as XNOR, here we focus on analog IMC architectures due to their great potential for achieving outstanding energy efficiency. For instance, Imec, a world-leading research and innovation hub in nanoelectronics, has recently provided a blueprint towards 10,000 tera operations per second per watt (TOPS/W) DNN inference in [8], which is based on the memristive-based analog IMC architectures.

Despite the potential benefits of the analog IMC architectures, one of the major factors limiting their wide use in practical ML applications is the large and energy-hungry signal conversion units required to change the computation domain from analog-to-digital (and vice versa) to compute the non-linear vector operations, e.g. activation functions in DNNs [9]. Recently, fully-analog IMC architectures are introduced that use memristive technologies to realize both MVM operations and activation functions within the same memory array [10]. These architectures remove the need for the signal conversion unit through maintaining the computation in the analog domain across various layers of DNNs and achieve significant energy and performance improvements. However, due to the fully-analog characteristic of these circuits, interconnect parasitics can have a major impact on the reliability and accuracy of the results obtained by these architectures. Thus, in this paper, we investigate the effect of interconnect parasitics on accuracy of fully-analog IMC architectures and propose an analog partitioning approach to resolve the parasitics effects while keeping the computation in the analog domain.

Figure 1 shows a schematic of the fully-analog IMC architectures, which includes a network of tightly coupled subarrays interconnected through programmable switch blocks. Each IMAC subarray consists of memristive crossbar, differential amplifiers, and neuron circuits, as shown in Fig. 1 (b). The memristor crossbars compute the MVM operation in DNNs in the analog domain through various physical mechanisms such as Ohm’s law and Kirchhoff’s law in electrical circuits [11]. In particular, the multiplications are performed according to the Ohm’s law ($I=GV$), and the accumulation operation is based on the conservation of charge described by the Kirchoff’s current law as expressed in the following equation, $I_{j}=\sum_{j}G_{ij}V_{i}$, where G_ij is the conductance of the resistive devices between neurons i and j, $I_{j}$ is the input current of post-synaptic neuron j, and $V_{i}$ is the output voltage of pre-synaptic neuron i.

Each positive and negative weight can be realized through adjusting the relative conductance of two memristive devices that are connected to a differential amplifier. As shown in Fig. 1 (b), differential amplifiers are connected to two consecutive rows in the crossbar, i.e. representing positive and negative weights, and generate an output current of $I_{O,i}=\sum_{k=1}^{n}(I_{k,i}^{+}-I_{k,i}^{-})$ for the $i$th row, where $n$ is the total number of input nodes in the layer. Whereas $I_{k,i}^{+}\propto V_{k}G_{k,i}^{+}$ and $I_{k,i}^{-}\propto V_{k}G_{k,i}^{-}$, thus, $I_{O,i}\propto\sum_{k=1}^{n}V_{k}(G_{k,i}^{+}-G_{k,i}^{-})$, in which $G_{i}^{+}$ and $G_{i}^{-}$ are the conductance of resistive devices that are shown in green and red color in Fig. 1 (b), respectively. Finally, the outputs of the differential amplifiers are connected to the analog neurons to compute the activation functions. In this architecture, each subarray computes both MVM operations and neurons’ activation functions in a single DNN layer and passes the result to its downstream neighbor IMAC subarrays that can compute the next layer.

Parasitic interconnect resistance ($R_{W}$) and capacitance ($C_{W}$) are a function of wire geometry and material properties of interconnections in analog IMC subarrays. Scaling up the size of arrays increases $R_{W}$ and $C_{W}$ leading to an increase in the latency of IMC circuits, thus limiting their operating clock frequency. Furthermore, increasing $R_{W}$ reduces the read margin that can impact the accuracy of analog IMC circuits [12]. Figure 2(c) shows the parasitic model for one bitcell in the IMC array. We use the most common equation to find the parasitic resistances for interconnects:

The parasitic capacitances play major roles in determining the latency of analog IMC circuits. To obtain good accuracy, we fixed the sampling time at 1ns considering the overall latency due to the addition of parasitic capacitances. We use the Sakurai-Tamaru model [19] for calculating the parasitic capacitance per length:

As the interconnect parasitic impacts can severely degrade the accuracy of the fully-analog IMC circuits, we propose an analog horizontal and vertical partitioning technique to decrease $R_{W}$ and $C_{W}$ without requiring to convert the signals from analog domain to digital. Figures 2 (a) and 2 (b) provide a schematic of the horizontal and vertical partitioning circuitry, respectively. For the horizontal partitioning, a layer of demultiplexers (DEMUX) is added to the output of the crossbars, which distributes the output currents corresponding to the matrix-vector multiplication results to either neurons in the same subarray for normal non-partitioned operation, or to the next subarray as partial products of that particular partition. Moreover, we locate switches on the output of the crossbars before DEMUX circuits to identify whether the generated output currents should be accumulated with the currents arriving from other subarrays (i.e. partitions) or not. Using these peripheral circuitry and necessary signaling to control the switches and DEMUX circuits, IMC circuit can handle the horizontal partitioning in the analog domain. Figure 2 (a) shows an example of horizontal partitioning with two partitions $H_{P}=2$. For vertical partitioning, an $n\times m$ array is divided into multiple $n\times k_{i}$ subarrays, in which $m=\sum_{i=0}^{V_{P}}k_{i}$, where $V_{P}$ is the total number of vertical partitions. Figure 2 (b) shows a sample of vertical partitioning with $V_{P}=2$.

In this section, we implement a $400\times 120\times 84\times 10$ DNN in SPICE circuit simulator for MNIST [20] handwritten image classification with 20$\times$20 pixels. We use the 14nm High-Performance PTM-MG FinFET model [21] along with the $VDD$ and $VSS$ voltages of 0.8V and -0.8V, respectively. Based on the 18nm gate length and the 22nm Fin height of the PTM 14nm FinFET model [22], the layout design parameter $\lambda$ and the metal thickness are fixed to 9nm and 22nm, respectively.

Here, spin orbit torque MRAM (SOT-MRAM) device model [23] is utilized to implement both synaptic structures and activation functions, as shown in Fig. 3 and Fig. 4, respectively. We use an analog sigmoidal neuron that includes two resistive devices and a CMOS-based inverter [10]. The resistive devices in the neuron’s circuit create a voltage divider that reduces the slope of the linear operating region in the inverter leading to a smooth high-to-low output voltage transition, which enables the realization of a $sigmoid$ activation function.

First, we study the effect of partitioning on accuracy and power consumption of the $400\times 120\times 84\times 10$ DNN implemented on a fully-analog IMC circuit. We select the number of partitions for each layer based on various dimensions of IMC subarrays, as listed in Table I. For instance, every layer in the targeted DNN can be deployed on an IMC architecture with $512\times 512$ subarrays without any partitioning, while if we use $256\times 256$ subarrays, the first layer that includes 400 inputs must be divided into two horizontal partitions to fit into two $256\times 256$ subarrays. The results listed in Table I show that without partitioning the deployed model fails to provide reliable classification. It can be seen that as the number of horizontal and vertical partitions increases, the accuracy improves due to the decrease in the length of the interconnects, and consequently their parasitic resistances. However, this is achieved at the cost of increased power consumption due to the extra circuitry added to handle partitioning.

The last row of Table I shows the results for a highly-partitioned case with $H_{P}=[16,8,8]$ and $V_{P}=[8,8,1]$ horizontal and vertical partitions for each layer, respectively. This means that assuming an analog IMC architecture with $32\times 32$ subarrays, the deployed model does not use the entire capacity of the subarrays, as shown in Fig. 5 (b). This deployment scenario results in a high accuracy of 94.84%, which is close to the $\sim$97% accuracy realized by the full-precision digital implementations on CPU. However, it is achieved at the cost of higher power consumption and more distributed deployment of DNN model on the architecture that leads to a higher area utilization.

Finally, we investigate the impact of bitcell size on the accuracy and power consumption of the analog IMC circuits. The distance between the wires and the length of the metal lines in an analog IMC subarray depends on the size of the synapse bitcell, which affects the interconnect parasitic resistances and capacitances as described in Section III. Figure 6 shows a non-ideal layout design for the SOT-MRAM based synapse, which leads to a larger bitcell area compared to what is realized in Figure 3. Table II provides the accuracy and power consumption results for various partitioning scenarios for the $400\times 120\times 84\times 10$ DNN workload deployment on an analog IMC architecture with non-ideal synapse layout design. Accuracy comparisons show that a $\sim$55% accuracy drop for the non-ideal IMC architecture with $H_{P}=[7,2,2]$ and $V_{P}=[2,2,1]$ partitions can reduce to less than 1% accuracy drop for the highly-partitioned scenario with $H_{P}=[16,8,8]$ and $V_{P}=[8,8,1]$ partitions. This shows that increasing the number of partitions can potentially compensate for the imperfections in the layout design at the cost of higher power and area consumption.

Herein, we focused on the impacts of interconnect parasitics on the accuracy of DNN models deployed on the fully-analog IMC architectures. The initial simulation results show that without any mechanisms to resolve the parasitic effects, a $400\times 120\times 84\times 10$ DNN model can barely achieve 15% accuracy for MNIST classification. Thus, we proposed a horizontal and vertical partitioning mechanism to alleviate the parasitic impacts, while maintaining the computation in the analog domain. This is particularly important in fully-analog IMC architectures which are designed to remove the need for signal conversion units through implementing nonlinear activation functions as well as matrix-vector multiplications in the analog domain. Our proposed partitioning mechanism has shown to be effective to diminish the parasitic impacts such that more than 94% accuracy could be realized for two different ideal and non-ideal layout design for the IMC circuit.