Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices

Magnetic Tunnel Junction (MTJ) consists of two ferromagnetic (FM) layers and an oxide layer that serves as a barrier between the two ferromagnetic layers [12]. The magnetization of one of the FM layers is fixed in most circuit applications of MTJs, while the other FM layer is free to take either a parallel or antiparallel magnetization [13]. This can be seen in Figure 2 as the bottom layer of the MTJ is fixed and the top layer is free to take a direction. If the MTJ shows a parallel magnetization ($R_{P}$) then it will have lower resistance than when it has an antiparallel magnetization ($R_{AP}$). [14]. The MTJ structure and two configurations are shown in Figure 2. The difference in resistance between the two states of the MTJ devices is given by the tunnel magnetoresistance ratio $TMR=(R_{AP}-R_{P})/R_{P}$. MTJ devices with higher TMR ratios have been shown to have higher reliability [15].

Figure 3 shows the general structure of an existing version of a Logic-In-Memory (LIM) based CMOS-MTJ circuit. The LIM architecture consists of a Pre-Charged Sense Amplifier (PCSA) circuit consisting of MP1, MP2, MN1, and MN2. A dual-rail NMOS only logic tree (T1-T4) evaluates the inputs and the non-volatile MTJs store data. The write circuit is used to switch the MTJs when the respective input is switched.

The operation of the PCSA can be explained through the existing PCSA based CMOS/MTJ XOR gate (Figure 6)[3] [16]. The PCSA, which uses a CLK signal, operates in two phases. The outputs are pre-charged to ”1” when CLK is set to ”0” and the output voltages begin to discharge to ground when CLK is set to ”1”. The discharge speed will be different for each branch due to the difference in resistance of the different MTJ configurations (parallel and antiparallel). For example, if MTJ1 is configured in parallel mode and MTJ2 is configured in antiparallel mode, then $R_{MTJ2}>R_{MTJ1}$. Due to the difference in resistances between $R_{MTJ1}$ and $R_{MTJ2}$, the discharge current through MTJ1 will be greater than MTJ2. When XOR reaches the threshold voltage of MP1, XNOR will be charged to “1” and XOR will be discharged to “0”.

Adiabatic logic is a circuit design technique for designing ultra-low-energy circuits [17]. Adiabatic logic reduces the energy of a circuit by recovering the energy stored in the load capacitor at the end of each clock cycle. The recovered energy is stored either through magnetic energy in clock inductors or through an electric charge in the clock capacitance. The recovered energy is then reused in the next cycle to reduce energy consumption. The energy dissipated in an adiabatic circuit is given by:

Where $T$ is the charging period of the capacitor, $C$ is the output load capacitor, $V_{dd}$ is the full swing of the power clock. If the charging time $T>2RC$, then the energy dissipated by an adiabatic circuit is less than a conventional CMOS circuit. Figure 5 illustrates the principle of energy recovery within an adiabatic system.

PRESENT [11] is an ultra-lightweight block cipher. PRESENT has low area when compared with other block ciphers which makes it a strong choice for implementation in area constrained IoT devices that look to be resilient against CPA attacks. In this paper, we intend to use the 80-bit version of PRESENT.

One of the components of PRESENT is the substitution box (S-box) which performs a non-linear substitution. When constructed with CMOS, the S-box consumes high energy and is prone to Correlation Power Analysis Attacks (CPA) thus we look to construct the S-box using our hybrid adiabatic-MTJ circuit. When constructing the S-box circuit using our proposed design we intend to limit the switching of MTJs to reduce energy consumption. To do this, we construct the S-box using a Look-Up-Table (LUT) based method in which the MTJs are written only once so that the output of the S-box is stored within the MTJs. Figure 8 illustrates our proposed S-box.

Another component of PRESENT is the XOR gate. As mentioned previously, MTJ circuits consume high power when there is frequent switching thus the XOR circuit cannot be designed with the proposed adiabatic-MTJ circuit. Instead, we have designed our XOR gate using 2-EE-SPFAL [18]. 2-EE-SPFAL has been shown to be CPA-resistant and low energy which allows the implementation of PRESENT to also be secure and low-energy. The complete implementation of PRESENT can be seen in Figure 10. The XOR gate can be seen in Figure 9.

The two criteria we will use to evaluate the security of our proposed design are Normalized Energy Deviation and Normalized Standard Deviation. The criteria Normalized Energy Deviation (NED) is defined as ($E_{max}$ - $E_{min}$)/$E_{max}$. NED is used to determine the percent difference between the minimum and maximum energy consumption. A second parameter, Normalized Standard Deviation (NSD), is defined as $\frac{\sigma_{e}}{\overline{E}}$ where $\sigma_{e}$ is the standard deviation of the energy dissipated by the circuit per input transition and $\overline{E}$ is the average energy dissipation. Both NED and NSD are important criteria when determining circuit resilience to CPA attacks. The lower the NED and NSD value the more uniform the power consumption and therefore the more secure a circuit is.

In this paper, we have calculated the NED and NSD values for our proposed S-box. Table II shows the NED and NSD values for our proposed design as well as a standard CMOS-based S-box as a base value to compare. From Table II we can see that our proposed design has lower average energy consumption than the CMOS-based S-box. Furthermore, our proposed S-box has lower NED and NSD values pointing towards its ability to defend against power analysis attacks.

A PRESENT S-box implemented with a hybrid adiabatic-MTJ circuit consumes uniform power and is therefore secure against Correlation Power Analysis (CPA) Attacks. Uniform power consumption from 1 round of PRESENT can be seen in Figure 11. The uniform power consumption is an indicator that the circuit is secure against a CPA attack as we will see when one is performed. MTJs are non-volatile memories that store data within the MTJs therefore, as a fair comparison we have added 64 Flip-Flops to the CMOS implementation to synchronize the inputs and store the output. Figure 12 and Table III shows the energy per cycle of the proposed hybrid adiabatic-MTJ circuit and CMOS implementations of 1 round of PRESENT. From Figure 12 and Table III we can see that our proposed design consumes 0.50 pJ/cycle at 5 MHz while the CMOS implementation consumes 0.80 pJ/cycle resulting in a 36.6% reduction in energy. At 50 MHz, our proposed design consumes 0.25 pJ/cycle while the CMOS implementation consumes 0.78 pJ/cycle resulting in a substantial energy reduction of 67.2%.

Previously we have shown our proposed hybrid adiabatic-MTJ based implementation of PRESENT to consume less energy when compared to CMOS. While reducing the energy consumption of a circuit we must also ensure the resilience of a circuit against side-channel attacks. The S-box of PRESENT will be the attack point in the Correlation Power Analysis (CPA) attack. The CPA attack is performed by following the steps described in [10]. The simulation was performed at 12.5 MHz with a 10fF load. Practical CPA attacks usually require a large amount of traces to steal encryption keys. However, we are performing a simulation without electrical noise and therefore we require much fewer traces to steal the encryption key. In our attack, we have chosen 80 samples per clock period thus we will sample every 1ns. Using 5120 input traces, we were able to steal the encryption key in the CMOS-based design of PRESENT-80. Figure 13(a) shows a successful CPA attack on a CMOS implementation of PRESENT-80.

While the CMOS key was revealed in 5120 traces, the hybrid adiabatic-MTJ implementation of the PRESENT S-box did not reveal the key in greater than 12,000 traces. Figure 13(b) shows an unsuccessful CPA attack against the hybrid adiabatic-MTJ implemented PRESENT S-box. This case study demonstrates our circuits resistance against CPA attacks and shows it is a promising candidate to design secure and low-energy IoT devices.