Microwave Engineering for Semiconductor Quantum Dots in a cQED Architecture

Gate defined quantum dots are a nascent platform for quantum computing in which electron charge and spin states are used to define the quantum bitHanson et al. (2007); Zwanenburg et al. (2013). In silicon and Si/SiGe heterostructures, recent work has shown it is possible to fabricate single, two, and four qubit systemsYoneda et al. (2018); Veldhorst et al. (2015); Kawakami et al. (2016); Zajac et al. (2018); Sigillito et al. (2019); Mi et al. (2018); Watson et al. (2018) with control infidelities at or approaching the $10^{-2}$ level requisite for error correctionFowler et al. (2012). For most quantum dot circuits, the control wiring scheme consists of an electron beam (e-beam) defined gate electrode structure with a rapid fan out into pads that are connected by aluminum or gold wire bonds to a printed circuit board (PCB) with typical die sizes of only a few millimeters. While this keeps the fabrication complexity to a minimum, it results in a minimally controlled microwave environment for the device and any readout circuitry. Near term quantum computing efforts with quantum dots face significant quantum systems engineering challenges balancing the needs for high fidelity readout, coupling, and control.

In this letter, we demonstrate a wiring scheme for quantum dot devices in a cQED architecture. This approach allows for high-density, low crosstalk wiring with controlled RF leakage characteristics, paving the way for larger quantum dot processors utilizing cQED techniques Mi et al. (2018); Stockklauser et al. (2017); Samkharadze et al. (2018). A simple and intuitive circuit model for cavity leakage from external leads reveals that minimization of the impedance of the environment at the cavity frequency ameliorates photon leakage out the gate leads, which otherwise present an undesired load on the cavity. We implement this method with a microstrip wiring scheme that achieves a low characteristic lead impedance of $Z_{g}\approx 10$ $\Omega$, and demonstrate resonators with quality factors as high as 8140 (design $Q_{L}=10^{4}$) while connected to the quantum dot gate stack.

For these experiments, we fabricate cavity-coupled pairs of triple quantum dot structures on an undoped Si/SiGe heterostructure using an overlapping aluminum gate stackZajac et al. (2015). The two dimensional electron gas (2DEG) is formed in a 9 nm thick strained silicon layer either 20 or 30 nm below the surface. To avoid accumulation of 2DEG under the resonator, we remove the heterostructure everywhere except for two 50 x 100 $\mathrm{\mu m}^{2}$ mesa regions on the sample where the dot structures are located. The circuit consists of four key components: the overlapping aluminum gate electrodes, the dot lead wiring, the superconducting $\lambda/2$ microwave resonator, and the resonator DC voltage tap. An optical image of a finished device is shown in Fig. 1 (a). To understand the control environment of the device, Fig. 1 (b) provides a simplified circuit diagram illustrating the key components the on-chip microwave engineering. Additional wires and parasitic cross capacitances are not drawn for simplicity. We confine the 2DEG into quantum dots using three layers of overlapping aluminum gates patterned with e-beam lithography (Fig. 1 (c)) and deposited by e-beam evaporation. High yield electrical isolation between gate layers is achieved by cleaning and oxidizing the aluminum after lift-off of each layer with a 250 W downstream oxygen plasma asher for 10 minutesDodson et al. .

Measurements of these samples are performed by wire bonding each device in a hybrid PCB-metal box enclosure designed to raise unwanted chip-mode frequencies to >20 GHz by creating a milled pocket below most of the 6.15 x 6.15 $\mathrm{mm}^{2}$ die Wenner et al. (2011). The packaged sample is cooled in a dilution refrigerator with base a temperature of $T_{\mathrm{mc}}=25\text{ mK}$ and typical electron temperatures between 80-100 mK determined by fitting to a thermally broadened conductance peakBeenakker (1991). Charge detection is achieved by measuring the cavity-charge interaction during electron tunneling eventsFrey et al. (2012); Mi et al. (2017). These interactions are formed by connecting a gate (in our case P2 in Fig. 1 (c)) to an aluminum or niobium microwave $\lambda/2$ resonator. Zero point fluctuations in the electric potential of the LC oscillator couple to the dipolar (quadrupolar) detuning degree of freedom ($\epsilon$) for the charge in the double (triple) dot system, allowing for detection of the quantum capacitance $C_{Q}\propto\frac{d^{2}E_{01}}{d\varepsilon^{2}}$. By probing the cavity with a microwave tone at the bare cavity frequency ($f_{r}$) and recording the transmitted amplitude and phase as a function of plunger gate voltage, damping and phase shifts of the probe are observed during electron tunneling events when the rates are comparable to the cavity frequency (of order several GHz). In the overlapping gate architecture, this condition is easily achieved through tuning of the dot barrier gate voltages B1-B4. Using the plunger gates P1-P3, we can empty out the electrons in a double (or triple) dot and reach the (0,0) (or (0,0,0)) charge state configuration, as demonstrated in Fig. 1 (d).

In order to maintain a high cavity quality factor we engineer the microwave environment to minimize photon leakage out the 25 bias leads of the two triple dot gate structures. This engineering amounts to maximizing the reflection coefficient of the microwave energy out any lead other than the readout port by making the other leads look like high or low impedance to ground. A unique requirement for cQED experiments with dots is DC voltage biasing of the center pin of the coplanar waveguide (CPW) resonator in order to accumulate a quantum dot under P2. Test devices with DC taps at the center of the waveguide had quality factors less than $10^{3}$, which was much lower than the explicit coupling defined by $C_{\text{in}}$ and $C_{\text{out}}$. We eliminate leakage out this lead by turning the tap into a $\lambda/4$-length CPW. The end of the $\lambda/4$ CPW is shunted with a load impedance $Z_{L}$ in the form of a large parallel plate capacitor using an $\text{SiO}_{2}$ dielectric. The input impedance for a $\lambda/4$ segment of transmission line terminated by a load $Z_{L}$ is given byPozar (2011)

where $\beta=2\pi/\lambda$ is the propagation constant of the transmission line, and $\ell$ is its physical length. By making the shunt capacitance large ($C_{\text{shunt}}\approx 100$ pF), we achieve $Z_{in}\approx 10\text{ k}\Omega$. In combination with tapping at the voltage node, this effective impedance leads to minimal leakage out the DC bias tap at the resonance frequency. Using this DC bias, devices without the overlapping aluminum gates achieved loaded quality factors as high as $4\text{x}10^{4}$, well beyond the limit imposed by parasitic loading from the quantum dot circuit. We note that the quadratic dependence of $Z_{\mathrm{in}}$ on $Z_{0}$ provides a way to further increase the quarter-wave tap input impedance through use of large $Z_{0}$ CPWsSamkharadze et al. (2018).

The use of the overlapping gate stack poses a unique challenge for RF readout schemes, because of the large parasitic capacitances $C_{p}$ (order 1 fF) between the gate electrodes in the region where the dots are formed. These parasitic capacitances are the same order of magnitude as the capacitance used to purposefully couple photons into the readout port ($C_{\text{out}}\approx 5.5$ fF for a quality factor of $10^{4}$ at 7.25 GHz) and therefore result in substantial microwave leakage out the leads. To analyze this leakage we first use a lumped element circuit model for loading of an LCR oscillator to a transmission line environment with characteristic impedance $Z_{g}$ and parasitic capacitance $C_{p}$ Pozar (2011); Göppl et al. (2008). We then extend this model to real circuits with finite length leads where the general transmission line impedance transformer behavior captured in Eq. (1) must be taken into account. After including finite length effects we show that the intuition from the lumped element model is qualitatively correct as long as dot gate lead lengths sufficiently avoid half integer multiples of the resonance wavelength $\lambda$ (e.g. $n\lambda/2$ for $n=0,1,2...$).

For the lumped element analysis, we write the resonator intrinsic quality factor as $Q_{i}=\omega_{\text{\emph{LC}}}\text{R}_{r}C_{r}$. Here $R_{r}$ is the effective damping resistance arising from the lossy dielectrics coupled to the electric field of the resonator. Schematically, each dot lead looks like the series combination of a capacitance $C_{p}$ and, in the limit of an infinite transmission line, an effective real impedance $Z_{g}$ to ground (Fig. 2 (a)). In the Norton equivalent circuit the gate impedance transforms to an additional parallel resistance

By computing the new total load resistance $R_{||}=R_{r}||Z_{g}^{*}$, we find the effective quality factor $Q_{\text{eff}}=\omega_{\text{\emph{LC}}}\text{R}_{||}C_{r}$. In terms of the impedance of the parasitic capacitor $Z_{c}$, gate impedance $Z_{g}$, and effective internal resistance $R_{r}$ we find:

revealing there are in principle two ways for reducing the effect of unwanted loading: minimize the parasitic capacitance (maximizing $Z_{c}$) or alter the gate impedance $Z_{g}$ to minimize the effect of the $R_{r}/Z_{g}$ term in the denominator of Eq. (3). Notably, it is easier to reach the limit of $Z_{g}\ll R_{r}$ than $Z_{g}\gg R_{r}$, as $R_{r}\gtrsim 10$ $\text{M}\Omega$ for typical superconducting resonators. Figure 2 (b) shows a contour plot of Eq. (3) in the low $Z_{g}$ regime. For our experiments, the characteristic cavity impedance is $Z_{r}=50$ $\Omega$, but the core result holds for higher impedance cavities as well and is captured by the definition of $R_{r}$.

Since reducing the parasitic capacitance in the overlapping gate stack is intrinsically difficult, we opt to control the gate impedance $Z_{g}$. Previous efforts to improve cavity quality factors involve the use of RF choke inductors or LC low pass filters, which have either high or low impedance at the cavity frequency, suppressing leakageFrey et al. (2012); Mi et al. (2017). In both cases, the leads acquire a frequency dependent filter function which substantially limits the control bandwidth. To eliminate this potentially undesired feature, we choose to reduce the characteristic impedance of the transmission line on-chip using a microstrip geometry. The design and implementation of microstrip wiring is illustrated in Fig. 2 (c). The wires are fabricated in a multilayer fabrication process that has three essential steps: deposition of the base layer ground plane, growth of an insulating dielectric layer, and deposition of the microstrip counter electrode.

To obtain the desired low impedance, we fabricate microstrips with a width $W=3$ $\mu\text{m}$ and an $\text{SiO}_{2}$ thickness $h=0.2$ $\mu\text{m}$ yielding the limit where the parameter $\alpha=W/h\gg 1$. The impedance of the microstrip in this limit can be calculated using conformal mapping and is given byK.C. Gupta (1996); Pozar (2011):

with an effective permittivity:

For our parameters, we find $Z_{g}\approx 10~\Omega$ which compares favorably to LC low pass filters in the literatureMi et al. (2017), that have an input impedance of $Z_{\text{in}}\approx 20~\Omega$, while retaining the flexibility of a flat frequency response. The low impedance leads come at the cost of an insertion loss of approximately 3.5 dB due to mismatch between the $Z_{0}=50$ $\Omega$ coaxial cabling and the $Z_{g}=10~\Omega$ microstrip. This effect could be mitigated by an impedance matching element such as a Klopfenstein taperK.C. Gupta (1996).

The multilayer stack also provides a means for improved and reliable microwave performance in increasingly complex processors through additional on-chip crossovers. These structures serve as low inductance connections between ground planes on-chip, thereby suppressing spurious slot line modes more efficiently than with traditional aluminum wire bond stitching Chen et al. (2014). Furthermore, aluminum wire bond stitching suffers from the low critical field of aluminum ($H_{c}\approx 10$ mT), which can damp the cavity upon application of an external magnetic fieldPetersson et al. (2012). Since both the crossover and base ground plane metals can be made of field tolerant superconductors such as niobium, they are useful for preserving circuit performance in cavity-spin coupling experiments. Lastly, in Fig. 2 (c) we demonstrate that this microstrip wiring scheme maintains less than -20 dB crosstalk between adjacent leads over a broad frequency range with a 7 $\mu$m wire pitch for approximately 1 mm, which could be important for minimizing off-resonant driving observed in recent resonant two-qubit gate experimentsZajac et al. (2018); Sigillito et al. (2019).

Using these design principles, we fabricated and measured over twenty cavity coupled quantum dot structures and found a total spread in resonance quality factors between 2600-8140 (example spectra shown in Fig. 2 (d)). We attribute the spread in quality factor to variation in parasitic capacitance and finite length effects for the low impedance microstrips (discussed below). We note that in addition to the spread in quality factors for identical resonator designs (with lithographic variation of order 0.2 $\mu\text{m}$), the fundamental resonance frequencies show a large spread of approximately $\pm 100$ MHz. Using the measured frequency, length of the waveguide, and conformal mappingK.C. Gupta (1996); Göppl et al. (2008) to estimate the capacitance of the CPW structure, we back out a mean substrate permittivity to be $\epsilon_{\text{r}}^{\text{SiGe}}\approx 14.2$. Using linear interpolationSchaffler (2001) we estimate the permittivity of the SiGe alloy to be $\epsilon_{\text{r}}(x)\approx\epsilon_{\text{r}}^{\text{Si}}(1-x)+\epsilon_{\text{r}}^{\text{Ge}}x\approx 13$ where $x=0.3$. The origin of the apparent deviation is unknown at this time. Variation in the observed resonance frequencies could be explained by variation in the relative dielectric constant of the SiGe alloy by $\pm 0.3$, possibly caused by fabrication processing or growth variation across the wafer.

Although Eq. (3) is correctGöppl et al. (2008); Pozar (2011) for coupling to an infinitely long transmission line with impedance $Z_{g}$, in practice the low impedance leads on-chip are only a few millimeters long and are wire bonded to a $50$ $\Omega$ environment. To elucidate the impact of the finite length of on-chip low impedance leads, we use "Simulation Program with Integrated Circuit Emphasis" (SPICE) to calculate the resonator line width under various conditions. Figure 3 (a) shows the circuit schematic used to understand the consequences of using finite transmission lines of length $\ell$. Similar to the lumped element case, lowering $Z_{g}$ and $C_{p}$ results in suppression of leakage. For a $\ell=1\text{ mm}$ microstrip, the contour plot of the leakage path impedance in Fig. 3 (b) is qualitatively similar to that in Fig. 2 (b), but the roll-off is stronger as a function of $Z_{\mathrm{g}}$.

In Fig. 3 (c,d) we compute $Q_{\mathrm{eff}}/Q_{\mathrm{L}}$ as a function of $Z_{\mathrm{g}}$ and leakage path (gate) length. When the gate length is a quarter wavelength of the resonance frequency, no voltage drop occurs across the $50$ $\Omega$ environment at the end of the lead, effectively eliminating loss out the lead. Conversely, when the lead is exactly $\lambda/2$ in length, the voltage drop across the $50$ $\Omega$ environment is maximal, resulting in loss to the environment equivalent to using no leakage suppression scheme at all. As shown in Fig. 3(c,d), if $Z_{g}$ is low, the range of gate lead lengths that suppress leakage becomes very wide, with only lengths very close to $\lambda/2$ displaying any significant degradation in $Q_{\mathrm{eff}}$. Figure 3 (e,f) shows that analogous results hold for $Q_{\mathrm{eff}}$ as a function of $C_{p}$. The inset to Fig. 3 (c) shows the reflection coefficient of a 50 $\Omega$ terminated transmission line calculated using Eq. (1). The result is very similar to the SPICE calculation in the main panel, and thus the simple analytic form provides good intuition for the finite length effects in maintaining a high Q.

In conclusion, we demonstrated a high-density, low-crosstalk, low impedance wiring scheme for quantum dots in a cQED framework. Using a simple circuit model we designed a filterless low impedance wiring strategy for minimal microwave leakage achieving quality factors as high as 8140. We showed how this approach remains robust even in the presence of finite length effects of the low impedance leads. For devices with functional quantum dots, measurement of the charge configuration down to zero electrons in both double and triple dots is achieved, paving the way towards study of spin-photon coupling of exchange-based qubits in Si/SiGe Russ, Petta, and Burkard (2018).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

We acknowledge discussions on multilayer superconducting circuit fabrication with A. Opremcak, E. Leonard, M. Beck, F. Schlenker, and M. Vinje. We acknowledge technical advice in development of processing recipes by K. Kuptcho, Q. Leonard, and E. Gonzales. Research was sponsored in part by the Army Research Office (ARO) under Grant Numbers W911NF-17-1-0274 and by the Vannevar Bush Faculty Fellowship program under ONR grant number N00014-15-1-0029. We acknowledge the use of facilities supported by NSF through the UW-Madison MRSEC (DMR-1720415) and the MRI program (DMR–1625348). The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Office (ARO), or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein.