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QECC-Synth: A Layout Synthesizer for Quantum Error Correction Codes on Sparse Hardware Architectures

Keyi Yin keyin@ucsd.edu University of California, San Diego, CA, USA Hezi Zhang hez019@ucsd.edu University of California, San Diego, CA, USA Xiang Fang x8fang@ucsd.edu University of California, San Diego, CA, USA Yunong Shi shiyunon@amazon.com Amazon Braket, New York, NY, USA Travis Humble humblets@ornl.gov Oak Ridge National Laboratory, Oak Ridge, TN, USA Ang Li ang.li@pnnl.gov Pacific Northwest National Laboratory, Richland, WA, USA Yufei Ding yufeiding@ucsd.edu University of California, San Diego, CA, USA
Abstract

Quantum Error Correction (QEC) codes are essential for achieving fault-tolerant quantum computing (FTQC). However, their implementation faces significant challenges due to disparity between required dense qubit connectivity and sparse hardware architectures. Current approaches often either underutilize QEC circuit features or focus on manual designs tailored to specific codes and architectures, limiting their capability and generality. In response, we introduce QECC-Synth, an automated compiler for QEC code implementation that addresses these challenges. We leverage the ancilla bridge technique tailored to the requirements of QEC circuits and introduces a systematic classification of its design space flexibilities. We then formalize this problem using the MaxSAT framework to optimize these flexibilities. Evaluation shows that our method significantly outperforms existing methods while demonstrating broader applicability across diverse QEC codes and hardware architectures.

I Introduction

Current quantum devices [1, 2, 3] suffer from errors, limiting their effectiveness in various applications [4, 5]. Quantum error correction (QEC) addresses this issue by encoding redundant physical qubits into logical qubits [6]. These logical qubits exhibit significantly lower error rates, ensuring the fidelity of quantum computations [7, 8]. Recent advancements in small-scale QEC implementations [9, 10, 11] demonstrate progress toward large-scale FTQC.

The core of QEC lies in the error syndrome measurement (ESM) circuits constructed from the QEC codes [12, 13, 14, 15, 16, 17, 18]. A typical ESM circuit (Fig. 1(a)) includes an syndrome qubit (red) and multiple data qubits (blue). Controlled gates (yellow) entangle the syndrome qubit with the data qubits, allowing errors on the data qubits to affect the syndrome qubit’s state and flip its measurement outcome, indicating error occurrence. Hundreds or even more such ESM circuits are executed in a QEC cycle to gather error information across the logical qubit spanning numerous data qubits. For example, a typical distance-2525 surface code has 625625 data qubits per logical qubit and needs 624624 such ESM circuits in a QEC cycle. This QEC cycle repeats during the runtime to safeguard the quantum system against errors.

However, implementing these circuits on current hardware presents a great challenge due to the mismatch between code topology and hardware architecture [19, 20, 21, 22, 23]. For instance, surface codes [18], a well-studied QEC code, requires a qubit connectivity of degree 44 (Fig. 1(b)) to enable interactions between the syndrome qubit (red) and four data qubits (blue) in their ESM circuits (Fig. 1(a)). In contrast, current hardware (Fig. 1(c)) typically has sparser architectures with connectivity degrees of 22 or 33 [24, 25, 5, 10, 26, 27] due to technical constraints [28, 29, 30]. Given the variety of QEC codes and hardware architecture, this gap is expected to persist in the foreseeable future.

A natural approach to tackle this issue involves swapping-based methods used in qubit mapping and routing (QMR) problems [31, 32, 33]. They insert SWAP gates into circuits to route distant qubits adjacent for interaction. For example, in Fig. 1(a), to execute a controlled-P4P_{4} gate between the syndrome qubit and distant data qubit q4q_{4}, a SWAP gate is used to relocate q4q_{4} to q3q_{3}’s position. However, altering qubit locations with these methods is unsuitable for ESM circuits because the QEC process requires consistent data qubit positions for repeated execution [34]. A potential solution is to enforce fixed data qubit locations as in Fig. 1(e). However, achieving this reliably with current methods may require exponentially increasing attempts as QEC circuit complexity grows.

Beyond swapping-based methods, theoretical research [35, 20, 36, 37] introduces ancilla qubits in circuit mapping to form an “ancilla bridge” that connects data qubits (marked red in Fig. 1(f)), termed bridging methods. Compared to swapping-based methods, they fix the qubit locations and use fewer CNOT gates (2 CNOTs compared to 3 CNOTs in a SWAP gate). However, current research primarily focuses on theoretical aspects and has made limited attempts only on manual designs targeting specific codes and architectures, mostly for small-scale problems. For instance, [35] manually implement the 7-qubit Steane code on a square lattice, while heuristic methods [19, 20] adapt the surface code [18] to regular lattices like heavy-hexagon [20] up to distance 5. These specific manual designs lack adaptability to newer QEC codes like qLDPC codes [38, 39] and future hardware architectures. Moreover, these methods assume ideal hardware structures and struggle with variations caused by defective qubits [40, 41, 42], an issue gaining recent attention [43, 44].

Refer to caption
Figure 1: Overview of QEC code synthesis. (a) A ESM circuit for error syndrome extraction. (b) The code topology associated with the ESM circuits. (c) A quantum hardware with sparse architecture. (d) Implementation of swapping-based method. (e) Implementation of swapping-based method with fixed data qubits. (f) Implementation of bridging method.

We identified a crucial oversight in previous bridging methods: neglecting the broad design space enabled by ancilla qubits. Theoretically, bridging methods allow for diverse ancilla bridge shapes and sizes, various ancilla sharing designs, and flexible gate scheduling (Section III). However, current methods rely on heuristic and manual designs, missing out on these flexibilities. This severely restricts the range of potential solutions, essentially limiting their generality.

Based on this insight, we introduce QECC-Synth, the first automated compiler for mapping ESM circuits using bridging methods applicable to diverse QEC codes and hardware architectures. To achieve this, we for the first time systematically categorize the flexibility of bridging methods into two key aspects: (1) ancilla bridge and (2) circuit optimization (Section III). We then identify two critical metrics for selecting optimal solutions related to these flexibilities: (1) extra CNOT gates in ancilla bridge construction and (2) total circuit depth. Minimizing these metrics is crucial for reducing physical errors and decoherence, thereby improving circuit fidelity. Therefore, we formalize the ESM circuit mapping into two optimization problems: code topology mapping and gate scheduling (Sections V-A and V-B), targeting the above two metrics. By translating code structures, hardware architectures, and mapping/scheduling conditions into Boolean constraints, we frame these optimization problems into MaxSAT framework, solvable by SAT solvers [45]. Importantly, our unified approach accommodates diverse codes and hardware setups, including systems with defective qubits. Furthermore, to handle large-scale problems, we introduce a heuristic algorithm that partitions them into manageable sub-problems addressed by our MaxSAT framework (Section V-C).

We evaluate our method against three baselines: (1) Sabre (heuristic, swapping-based) [31], (2) SATmap (solver-based, swapping-based) [33], and (3) Surf-Stitch (heuristic, bridging-based, targeting surface codes) [19]. Our method achieves an average reduction of 74.9% and 26.5% in extra CNOT gate counts, and 34.7% and 55.5% in circuit depth compared to Sabre and SATmap, respectively. Our method also outperforms the surface-code-specific approach Surf-Stitch with 10% fewer extra CNOT gates and 38.5% shallower circuits. Additionally, these baselines frequently fail to provide solutions for special QEC codes and hardware setups and exceed memory limits for large-scale problems (Section VI). In contrast, our approach consistently identifies viable solutions.

Overall, we make the following contributions:

  • We introduce QECC-Synth, a bridging-based compiler for efficiently mapping ESM circuits, supporting diverse QEC codes and hardware architectures.

  • We pioneer the exploration of the expansive design space of bridging methods and formalize ESM circuit mapping as a two-stage MaxSAT problem.

  • We propose a heuristic approach based on our MaxSAT framework to effectively handle scalability challenges with large-scale codes.

  • Our evaluation shows that QECC-Synth outperforms existing swapping-based and bridging-based methods across various QEC codes and hardware setups, while also demonstrating good scalability.

II Background

In this section, we provide essential background information on ESM circuits implementation.

II-A ESM Circuits for Stabilizer Codes

We focus on stabilizer codes [6, 46] that encompass most extensively studied QEC codes [47, 48, 18].

Refer to caption
Figure 2: (a) The stabilizer structure and error syndromes of the Steane code [13]. (b) ESM circuit for the stabilizer X1X2X3X4X_{1}X_{2}X_{3}X_{4} with a single syndrome qubit. A ZZ-error on q3q_{3} will flip the measurement result of the syndrome qubit.

Stabilizer codes. Stabilizer codes are characterized by a set of stabilizers, which are Pauli strings of the form P1P2PmP_{1}P_{2}\dots P_{m}, where Pi{I,X,Y,Z}P_{i}\in\{I,X,Y,Z\} denotes a Pauli operator acting on qubit qiq_{i}. For instance, Fig. 2(a) gives a stabilizer code with stabilizers {s1=X1X2X3X4,s2=X2X4X5X6,s3=X3X4X6X7}\{s_{1}=X_{1}X_{2}X_{3}X_{4},s_{2}=X_{2}X_{4}X_{5}X_{6},s_{3}=X_{3}X_{4}X_{6}X_{7}\}. Each stabilizer collects error information on its involved qubits, and combining this information from all stabilizers helps to deduce the type and location of errors, facilitating appropriate corrections. In practice, this process of error information collection involves implementing a dedicated error syndrome extraction (ESM) circuit for each stabilizer.

ESM circuits. The ESM circuit of a stabilizer comprises a syndrome qubit (red) and several data qubits (blue), connected by controlled gates specified by the stabilizer. The syndrome qubit is initially set to the |0|0\rangle state and is measured at the end. If there are no errors on the data qubits, the measurement outcome is still 0. Conversely, certain errors on the data qubits will propagate through the controlled gate to the syndrome qubit, flipping its measurement outcome from 0 to 11, indicating error occurrence. For instance, as shown by the red dashed line in Fig. 2(b), a ZZ-error on qubit q3q_{3} propagates through the CNOT gate and flipsthe measurement outcome of s1s_{1}. Notably, stabilizers often share data qubits, which introduces complexity to the mapping and scheduling of their ESM circuits (more details in Section III).

Error detection and correction. During a QEC round, each ESM circuit is executed once. Their measurement results consist error syndromes that guide error correction. For instance, in Fig. 2(a), the error syndrome (s1,s2,s3)=(1,0,1)(s_{1},s_{2},s_{3})=(1,0,1) suggests a ZZ-error on qubit q3q_{3}, which can be corrected by applying a ZZ gate to q3q_{3} since Z2=IZ^{2}=I. Crucially, all ESM circuits can theoretically operate in parallel within a QEC round due to the commutativity of stabilizers, allowing for a larger optimization space for scheduling (more details in Section III).

II-B Bridging method

ESM circuits necessitate interactions between the syndrome qubit and all data qubits, which is challenging with hardware of limited connectivity. The bridging method [35] offers a promising solution by extending the syndrome qubit with additional ancilla qubits called bridge qubits, forming an “ancilla bridge” that connects distant data qubits. This approach resolves connectivity issues while maintaining error syndrome extraction as in the original ESM circuit.

Mitigating connectivity issue. In bridging method, the ancilla bridge is prepared in a special entangled state [49] by inserting additional CNOT gates (highlighted in red). This state ensures that the controlled gates acting on the syndrome qubit can be transferred to the bridge qubit while maintaining circuit equivalence. As a result, the connectivity requirements, originally concentrated on the single syndrome qubit, are now distributed across multiple bridge qubits, thereby reducing the overall connectivity demand. For instance, the circuit with a length-2 ancilla bridge in Fig. 3(b) only requires each qubit to connect to at most 3 others, compared to 4 in Fig. 2(b), allowing for a direct mapping to current sparse quantum architecture [24, 25, 5, 26].

Refer to caption
Figure 3: Bridging method. (a) The connectivity of the bridging-based ESM circuit. (b) Red line: This construction maintains error detection. Blue line: The inserted CNOT gate may introduce more error leading to error syndromes.

Error syndrome extraction. Remarkably, the ancilla bridge construction ensures that errors on the data qubits trigger a flip in the measurement result of the syndrome qubit, just as in the original ESM circuit (Fig. 2(b)). This occurs because errors can still propagate to the syndrome qubit through the special entangled state of the ancilla bridge (GHZ state). For instance, in Fig. 3(b), a ZZ-error on q3q_{3} still flips the measurement result of the syndrome qubit s1s_{1} (as shown by the red dashed line). Consequently, the transformed ESM circuit with bridge qubits preserves the same error detection and correction capabilities as the original circuit.

Refer to caption
Figure 4: Flexibility of the bridging method for ESM circuits synthesis. (a) Code Topology Mapping: The ancilla bridges of different stabilizer may have different size, shape and may share ancilla qubits. (b) Circuit Scheduling: The scheduling need to consider ESM commutativity, equivalent state preparation on ancilla bridges and correct circuit parallelism.

Impact of extra CNOT gates. Bridging methods introduce additional CNOT gates (highlighted in red) compared to the original ESM circuit (Fig. 2(b)). Similar to the extra CNOT gates in SWAP-based methods, these CNOTs can introduce errors to data qubits, potentially increasing the logical error rate. For example, in Fig. 3(b), if a YY-error occurs due to an introduced CNOT gate (within the block), it can induce a correlated two-qubit XXXX error on data qubits and affect the accuracy of the syndrome measurement. Therefore, minimizing the number of CNOT gates is crucial to mitigate these detrimental effects.

III Motivating Examples

In this section, we provide examples to illustrate the vast design space of bridging-based ESM circuit mapping and scheduling. We highlight two main flexibilities: (1) varying ancilla bridges to optimize qubit mapping with fewer CNOT gates, and (2) leveraging circuit commutativity and equivalence to optimize gate scheduling for reduced circuit depth.

III-A Flexibility of Code Topology Mapping

Ancilla bridges offer significant flexibility, particularly in terms of (1) various shapes and sizes and (2) shared ancilla qubits. This flexibility helps to find an effective mapping of the stabilizer code’s topology onto the architecture, including the data qubit mapping and the ancilla bridge allocation. Moreover, varying constructions can introduce different numbers of CNOT gates (Section II), impacting the fidelity of the synthesized ESM circuits. Since the total size of the ancilla bridge linearly correlates with the number of extra CNOT gates, we prioritize minimizing it as our optimization goal in code topology mapping (Section V).

(1) Various shapes and sizes. The flexibility of ancilla bridges extends to their shapes and sizes, which stems from their operational mechanism. As long as the ancilla bridge is initialized in an entangled state, errors on data qubits can propagate to the syndrome qubit regardless of which bridge qubit they are connected to. Thus, the circuit can extract the error syndrome, irrespective of the ancilla bridge’s shape or size. Consequently, the shape and size of the ancilla bridge can vary depending on the allocation of data qubits. For example, as shown in Fig. 4(a), both the 4-qubit and 5-qubit ancilla bridges for s1s_{1} and s3s_{3} can effectively fulfill their function, demonstrating this flexibility. For more details, we recommend referring to Lao et al. [35].

(2) Ancilla qubit sharing. Ancilla bridges for different stabilizers can share the same ancilla qubits, reducing the number of ancilla qubits required to be connected to a data qubit. For example, in Fig. 4(a), stabilizers s1s_{1} and s2s_{2} share two ancilla qubits in the middle row. Although this design saves qubits, ESM circuits sharing ancilla qubits cannot be executed simultaneously due to resource conflicts. This presents a challenge for gate scheduling to optimize parallel executions.

III-B Flexibility of ESM Circuit Scheduling

The distinctive structures of ESM circuits allow for more flexible optimizations in scheduling compared to the gate-level scheduling for general quantum circuits. This flexibility arises mainly from three aspects: (1) commutativity of stabilizer measurements, (2) equivalent state preparations on ancilla bridges and (3) parallel ESM circuits. Leveraging this flexibility, our goal is to identify a correct scheduling while minimizing the circuit depth.

(1) Commutable stabilizer measurements. Implementing a QEC code involves executing ESM circuit blocks (Fig. 2(b)) for all stabilizers. Theoretically, these ESM circuit blocks for various stabilizers commute, allowing for arbitrary permutations in their order. As illustrated in Fig. 4(b1), sequentially executing stabilizer blocks s1s_{1}, s2s_{2}, and s3s_{3} can be optimized by moving s3s_{3} to the front and executing it in parallel with s1s_{1}, leading to a substantial decrease in circuit depth.

(2) Equivalent state preparations on ancilla bridges. As explained in Section II, the ancilla bridge is initialized in an appropriate entangled state. This initialization can be accomplished through various circuits and some of which may offer smaller circuit depths [49]. For instance, in Fig. 4(b2), both circuits can prepare the 4-qubit initial state on the ancilla bridge of s1s_{1}, but the second one has a smaller circuit depth.

(3) Parallel ESM circuits. Although two ESM circuits can be executed in parallel as long as their ancilla bridges do not overlap, the overlap on data qubits makes it impossible to arbitrarily order the controlled gates while still ensuring a correct error syndrome extraction. To illustrate, as depicted in Fig. 4(b3), the simultaneous measurement of two stabilizers Z1Z2Z_{1}Z_{2} and X1X2X_{1}X_{2}, which share two data qubits, poses a challenge for the scheduling of their controlled-ZZ and controlled-XX gates. While the second circuit provides correct measurement results, the first one can only yield random outcomes [18]. This necessity for correctness adds intricacy to scheduling and must be addressed accordingly.

IV Overview of QECC-Synth

This section outlines the workflow of our QECC-Synth framework. It splits into two paths based on problem size, as shown in Fig. 5. For small-scale problems, QECC-Synth utilizes our dedicated two-stage SAT solver (Fig. 5, left frame) to generate optimal ESM circuit implementations. For large-scale problems, we employ the relaxation technique of problem partitioning to resolve the scalability issue (Fig. 5, right).

IV-A Constraint-based Approach: Two-stage SAT

The left frame in Fig. 5 represents the central component of the QECC-Synth framework. It takes the stabilizer code and hardware architecture as inputs and generates the ESM circuit implementation, specifying both qubit allocation and scheduled circuit. Building on the two flexibility categories identified in Section III, we break down this problem into two stages of constraint-based optimization: Stage 1. Code topology mapping and Stage 2. ESM circuit scheduling.

Stage 1. Code Topology Mapping. This stage aims to map data qubits and allocate ancilla bridges based on the stabilizer code and hardware architecture. The code is represented by its stabilizer set Stab={s1,s2,}Stab=\{s_{1},s_{2},\cdots\}, where sis_{i} are Pauli strings acting on data qubits Data={q1,q2,}Data=\{q_{1},q_{2},\cdots\}, while the hardware architecture is represented by its coupling graph, with vertices being physical qubits Phys={P1,P2}Phys=\{P_{1},P_{2}\cdots\} and the edges Edges={e1,e2,}Edges=\{e_{1},e_{2},\cdots\} specifying their connectivity. The output consists of: (1) Data qubit mapping Π:DataPhys\Pi:Data\rightarrow Phys that map data qubits to physical qubits on hardware, (2) Ancilla bridge Anc:StabsSubsets of PhysAnc:Stabs\rightarrow\text{Subsets of }Phys that allocate an ancilla bridge for each stabilizer, and (3) Coupling relation CP:Stabs×DataPhysCP:Stabs\times Data\rightarrow Phys that specifies the ancilla qubit to which each data qubit connects in each stabilizer.

We address this problem using the MaxSAT framework. The validity of the output is ensured by various constraints (red frame), while optimality is pursued by maximizing an objective function composed of a weighted sum involving multiple optimization goals (blue frame). For instance, we minimize the overall size of ancilla bridges, which directly impacts the number of introduced CNOT gates (Section III), and maximize the number of compatible stabilizers to enable parallel execution. The corresponding objective function is:

w1#{Ancillaqubits}+w2#{Compatible anc. bridge pairs}\begin{split}-w_{1}\cdot\#\left\{\begin{aligned} &\text{Ancilla}\\ &\text{qubits}\\ \end{aligned}\right\}+w_{2}\cdot\#\left\{\begin{aligned} &\text{Compatible anc.}\\ &\text{\quad bridge pairs}\\ \end{aligned}\right\}\end{split}

Adjusting the weights w1,w2w_{1},w_{2} alters the priority of optimization goals. The detailed MaxSAT encoding of constraints and objective function will be elaborated in Section V.

Refer to caption
Figure 5: Overview of QECC-Synth.

Stage 2. Gate Scheduling. This stage aims to find a gate scheduling with minimal circuit depth, based on the qubit allocation determined in Stage 1. The output is a mapping Sche:Circuits{1,2,}Sche:Circuits\rightarrow\{1,2,\cdots\} that assigns each gate gCircuitsg\in Circuits a time step for execution. The search process is encoded into a SAT solver, with constraints (detailed in Section V) specified to ensure scheduling validity. To minimize circuit depth, we iteratively query the SAT solver with decreasing requirements on circuit depth until no solutions are found. This iterative approach helps obtain increasingly better solutions with smaller circuit depths, finally leading to a solution with minimal depth.

The outputs of the above two stages together constitute the complete output of our framework, specifying the mapping of data qubits and ancilla bridges, as well as the time schedule of each gate in the ESM circuit.

IV-B Heuristic Approach: Code Partitioning

The optimal approach described in Section IV-A faces challenges when applied to large-scale problems due to the escalating number of constraints. To address this scalability concern, we partition the stabilizer set SS of a code into smaller subsets S1,,SkS_{1},\cdots,S_{k} and leverage our two-stage optimal solver described in Section IV-A to find their implementations. This yields optimized ESM circuits CiC_{i} for each subset SiS_{i}. Subsequently, we sequentially execute these ESM circuits for sub-problems to generate the complete solution for the entire stabilizer code. SWAP gates are inserted between adjacent ESM circuits to reposition the qubits from the previous circuit CiC_{i} to meet the requirements of the next one Ci+1C_{i+1} (detailed in Section V). The evaluation (Section VI) shows that our approach enables scalability while yielding favorable results.

V Constraint-Based Code Synthesis

In this section, we delve into the technical aspects of SAT encoding for the two stages in QECC-Synth: code topology mapping and ESM circuit scheduling.

V-A Stage 1: Code Topology Mapping via MaxSAT

In this stage, we encode the mapping of data qubits and the allocation of ancilla bridges into a MaxSAT problem. We formulate the qubit location requirements as hard constraints and the objectives of minimizing the total ancilla bridge size and incompatible stabilizer count as soft constraints.

V-A1 Hard Constraints:

We list a few hard constraints that ensures the validity of qubit allocation.

Hard A. Basic Requirements. A legitimate qubit allocation should satisfy the following basic requirements.
(1) Each data qubit is mapped to a unique physical qubit:

pPhysmap(q,p)=1, for qData\displaystyle\sum_{p\in Phys}map(q,p)=1\text{,~{}for~{}}q\in Data
qDatamap(q,p)1, for pPhys\displaystyle\sum_{q\in Data}map(q,p)\leq 1\text{,~{}for~{}}p\in Phys

where map(q,p)=Truemap(q,p)=True if data qubit qq is mapped to physical qubit pp, and map(q,p)=Falsemap(q,p)=False otherwise.
(2) A physical qubit cannot serve as both a data qubit and an ancilla qubit simultaneously:

¬map(q,p)¬anc(s,p), for (q,s)Data×Stabs\displaystyle\neg map(q,p)\bigvee\neg anc(s,p)\text{,~{}for~{}}(q,~{}s)\in Data\times Stabs

where anc(s,p)=Trueanc(s,p)=True if physical qubit pp is an ancilla qubit for stabilizer ss, and anc(s,p)=Falseanc(s,p)=False otherwise.

Hard B. Connectivity of ancilla bridge. The ancilla bridge for each stabilizer needs to form a connected graph. To ensure this, we employ breadth-first traversal (BFT) [50]. All physical qubits in the connected Graph[Anc[s]]Graph[Anc[s]] must be visited within a specified parameter L[s]L[s], representing the maximum size of the ancilla bridge Anc[s]Anc[s] for stabilizer ss. We introduce auxiliary variables vs,p(pi,t)v_{s,p}(p_{i},t) to track whether physical qubit pip_{i} has been visited after the tt-th round (t{1,,L[s]}t\in\{1,\dots,L[s]\}). In the initial round, we ensure that the starting vertex is visited:

vs,p(p,1)pip¬vs,p(pi,1)\displaystyle v_{s,p}(p,1)\bigwedge_{p_{i}\neq p}\neg v_{s,p}(p_{i},1)

In subsequent rounds, an unvisited physical qubit pip_{i} in the ancilla bridge Anc[s]Anc[s] is visited if any of its adjacent qubits pjp_{j} have been visited in the previous rounds:

vs,p(pi,t)\displaystyle v_{s,p}(p_{i},t) anc(s,pi)\displaystyle\rightarrow~{}anc(s,p_{i})
[vs,p(pi,t1)pjAdj(pi)vs,p(pj,t1)]\displaystyle\wedge\left[v_{s,p}(p_{i},t-1)\bigvee_{p_{j}\in Adj(p_{i})}v_{s,p}(p_{j},t-1)\right]

To ensure that the traversal starts from any possible physical qubit, we enforce constraints for each pPhysp\in Phys:

anc(s,p)piPhys(¬anc(s,pi)vs,p(pi,L[s]))\displaystyle anc(s,p)\rightarrow\bigwedge_{p_{i}\in Phys}(\neg anc(s,p_{i})\vee v_{s,p}(p_{i},L[s]))

The number of variables and the conjunctive normal form (cnf) clause used for each stabilizer are both O(L[s]|Stabs|2)O(L[s]*|Stabs|^{2}).

Hard C. Coupling between data and ancilla qubits. Each data qubit for stabilizer ss must be directly coupled to some ancilla qubit in its ancilla bridge Anc[s]Anc[s]:
(1) Exactly one ancilla qubit pp is coupled with data qubit qq:

pPhyscp(s,q,p)=1, for qData[s]\displaystyle\sum_{p\in Phys}cp(s,q,p)=1\text{,~{}for~{}}q\in Data[s]

(2) The coupling relation CP(s,q)=piCP(s,q)=p_{i} requires qq to be mapped to some qubit pip_{i} adjacent to pp:

cp(s,q,p)piAdj(p)map(q,pi)anc(s,p)\displaystyle cp(s,q,p)\rightarrow\bigvee_{p_{i}\in Adj(p)}map(q,p_{i})\bigwedge anc(s,p)

V-A2 Soft Constraints:

We introduce several soft constraints to optimize the performance of ESM circuit implementation. Each soft clause is assigned a non-negative weight indicating its priority, and a MaxSAT solver is used to obtain a solution that maximizes the sum of the weights of all satisfied soft clauses.

Soft P1. Minimizing the total ancilla bridge size. Reducing the total ancilla bridge size compresses the ESM circuit and minimizes the introduced extra CNOT gates, enhancing circuit fidelity. This is achieved by maximizing the number of Boolean variables anc(s,p)anc(s,p) set to FalseFalse. Hence, we add the following soft constraints with weight P1P1:

¬anc(s,p), for (s,p)Stabs×Phys\displaystyle\neg anc(s,p)\text{,~{}for~{}}(s,p)\in Stabs\times Phys

Soft P2. Mitigating the stabilizer conflicts. Stabilizers without conflicts in ancilla qubits can be efficiently executed in parallel, termed as compatible stabilizers. Our aim is to maximize the count of compatible ancilla bridge pairs. Thus, we introduce the following soft constraints with weight P2P2:

pPhys¬anc(s,p)¬anc(s,p), for s,sStabs\displaystyle\bigwedge_{p\in Phys}\neg anc(s,p)\vee\neg anc(s^{\prime},p)\text{, for }s,s^{\prime}\in Stabs

Fig. 6 illustrates how different optimization objectives impact the mappings of the same code Stabs=X1X2X3,Z2Z3Stabs={X_{1}X_{2}X_{3},Z_{2}Z_{3}} onto a heavy square architecture. In the first row, Soft P1 is the primary objective, with weight P1P_{1} notably greater than P2P_{2}. Consequently, the resulting mapping features an ancilla bridge with size 11, yet two stabilizers share the same ancilla qubit. Conversely, in the second row, Soft P1 is prioritized, resulting in a mapping without conflicts in data qubits, albeit with a larger ancilla bridge size. In practice (Section VI), we prioritize Soft P1 over Soft P2, given its more significant impact on the overall error correction performance.

Refer to caption
Figure 6: Different mappings for stabilizer code {s,s}\{s,s^{\prime}\} with different optimization priority.

V-B Stage2: ESM Circuit Scheduling via SAT

This stage encodes the gate scheduling of ESM circuits into a SAT problem. We introduce additional Boolean variables to characterize all operations within the circuits (Section V-B1). These variables help to formulate constraints based on dependencies between operations, ensuring the validity of their scheduling (Section V-B2). Finally, we iteratively query the SAT solver to achieve a scheduling with minimal circuit depth.

Refer to caption
Figure 7: (a) Five stages of a typical ESM circuit with ancilla bridge. (b) Equivalence between encoding (decoding) circuit for ancilla bridge and tree transversal.

V-B1 Operations within ESM Circuits:

A ESM circuit with ancilla bridge typically comprises five phases: (1) Initialization, (2) Encoding, (3) Control, (4) Decoding, and (5) Measurement, as shown in Fig. 7(a). Operations in Phases (1)(3)(5) are determined by the output of Stage 1, which includes qubit allocation and coupling relations between ancilla and data qubits. Specifically, qubit allocation specifies all ancilla qubits initialized in the |0|0\rangle state, with the syndrome qubit measured at the end, constituting Phases (1)(5). The coupling relation precisely determines all CNOT gates in Phase (3). To characterize Phases (2)(4), we introduce the following Boolean variables:

1

enc(s,p,p)enc(s,p,p’) and dec(s,p,p)dec(s,p,p’): The variable enc(s,p,p)enc(s,p,p’) is set to TrueTrue if there is a CNOTCNOT gate from pp to pp’ in the Encoding phase for stabilizer ss, and FalseFalse otherwise. Similar definitions apply to dec(s,p,p)dec(s,p,p’). Additionally, a Hadamard gate is applied to the syndrome qubit. These Boolean variables collectively characterize the operations in Phases (2)(4).

2

time(g,t)time(g,t): This denotes the time assignment of operations gCircuitsg\in Circuits. If the operation gg is executed at time tt, time(g,t)time(g,t) is set to TrueTrue; otherwise, it is set to FalseFalse.

V-B2 Boolean Constraints for Gate Scheduling:

This section outlines the constraints that must be satisfied by a valid gate scheduling, using the variables defined above.

Hard A. Time Assignment Constraints. A valid gate scheduling should satisfy the following basic requirements regarding time assignments. We define TT as the maximum allowable circuit depth for the search.
(1) All gates should be executed exactly once:

ttime(g,t)=1, for gCircuits\displaystyle\sum_{t}time(g,t)=1\text{, for }g\in Circuits

(2) Two operations gg and gg^{\prime} act on the same physical qubit pp cannot be executed simultaneously. In other words, at most one operation acting on pp can be executed at time tt:

gAct[p]time(g,t)1, for t{1,,T}\displaystyle\sum_{g\in Act[p]}time(g,t)\leq 1\text{, for }t\in\{1,...,T\}

where Act[p]Act[p] denotes all the operations acting on pp.

Hard B. Valid Enc[s]Enc[s] and Dec[s]Dec[s] circuits. The circuits in the Encoding and Decoding phases should effectively encode and decode the GHZ state for the ancilla bridge. We observe that the encoding circuit’s formulation is analogous to a tree traversal, where the syndrome qubit serves as the root with an H gate acting on it, and other ancilla qubits are visited via CNOT links (Fig. 7(b)). The decoding circuit can be viewed as the mirror image of the encoding circuit. With this understanding, we establish the following constraints:

(1) The transversal tree must have exactly one root:

pAnc[s]enc(s,p,p)=1\displaystyle\sum_{p\in Anc[s]}enc(s,p,p)=1

where enc(s,p,p)enc(s,p,p) is set to TrueTrue if an H gate acts on physical qubit pp, and FalseFalse otherwise.

(2) Each node within the transversal tree is visited exactly once, ensuring that every ancilla qubit pAnc[s]p\in Anc[s] is subjected to exactly one CNOTCNOT gate targeting it:

piAnc[s]enc(s,pi,p)=1\displaystyle\sum_{p_{i}\in Anc[s]}enc(s,p_{i},p)=1

(3) The control qubit must be prepared before its associated CNOT gate is executed. Specifically, if gj=CNOT(pi,pj)g_{j}=CNOT(p_{i},p_{j}) and gi=CNOT(pk,pi)g_{i}=CNOT(p_{k},p_{i}), then gjg_{j} must be executed after gig_{i}:

enc(s,pi,pj)(tgi<tgj), for pipjAnc[s]\displaystyle enc(s,p_{i},p_{j})\rightarrow\left(t_{g_{i}}<t_{g_{j}}\right)\text{, for }p_{i}\neq p_{j}\in Anc[s]

Hard C. Correct order of Ctrl[s]Ctrl[s] circuits. The anticommuting controlled-PiP_{i} gates in the Control phase should satisfy a particular order to ensure the correctness of the circuit. Specifically, the order is correct if and only if the count of anti-commuting gate pairs (c,c)(c,c^{\prime}) satisfying tc<tct_{c}<t_{c^{\prime}} is an even number. This requirement is encoded into the constraint:

Anti(c,c)(tc<tc)=0, for cCtrl[s] and cCtrl[s]\displaystyle\bigoplus_{Anti(c,c^{\prime})}(t_{c}<t_{c}^{\prime})=0\text{, for }c\in Ctrl[s]\text{~{}~{}and~{}}c^{\prime}\in Ctrl[s^{\prime}]

where \bigoplus means the mod 2 addition and Anti(c,c)=TrueAnti(c,c^{\prime})=True means cc and cc^{\prime} anti-commute.

Hard D. Commutativity of incompatible stabilizers. Two stabilizer circuits ss and ss^{\prime} sharing ancilla qubits cannot he executed simultaneously. This constrain can be realized by requiring Init[s]Init[s] after Meas[s]Meas[s^{\prime}], Init[s]Init[s^{\prime}] after Meas[s]Meas[s]:

[pShare(tMz[p]<tInit[p])][pShare(tMz[p]<tInit[p])]\displaystyle\left[\bigwedge\limits_{p\in Share}(t_{Mz^{\prime}[p]}<t_{Init[p]})\right]\bigvee\left[\bigwedge\limits_{p\in Share}(t_{Mz[p]}<t_{Init^{\prime}[p]})\right]

where Share=Anc[s]Anc[s]Share=Anc[s]\cap Anc[s^{\prime}] represent all physical qubit that shared by two stabilizer’s ancilla block.

V-C Heuristic Approach

As previously discussed, the number of clauses increases exponentially with the number of stabilizers in a QEC code, creating a significant bottleneck in our framework. To address this challenge for large-scale QEC code synthesis, we propose a relaxation method that can still yield locally optimal solutions. Our approach involves partitioning the set of stabilizers and solving a SAT problem for each subset sequentially through our two-stage constraint-based approach. Finally, we insert routing layers between the these synthesized ESM circuits to integrate them into the original code.

Partitioning the stabilizer set. We can think of a stabilizer set SS as a union of subsets, S0SkS_{0}\cup\dots\cup S_{k}. However, due to the commutativity of the stabilizers, there are millions of possible partition choices. Since each stabilizer can be viewed as a set of constraints for the data qubits to satisfy, we want the constraints for the same data qubits to be in the same partition, allowing them to be handled together. It means to minimize the connections or shared qubits between stabilizers from different subsets. As a result, we formulate this as a simple balanced graph partitioning problem in graph theory [51]. For example, in the Steane code shown in Fig. 2(a), we treat each stabilizer as a vertex. As stabilizer s1s_{1} shares two data qubits, q2q_{2} and q4q_{4}, with stabilizer s2s_{2}, two edges will be added to the graph. The balanced graph partitioning divides the vertices into kk components of almost equal size, minimizing the capacity of edges between different components.

Sorting the SAT problems. After partitioning the stabilizer set, we can apply our two-stage SAT solver to synthesize the ESM circuit for each stabilizer subset. However, different resulting data qubit mappings can make it challenging to integrate them into a complete circuit for the original code. The mapping mapimap_{i} for subset SiS_{i} should follow the mappings from map0map_{0} to mapi1map_{i-1} as closely as possible, because stabilizers from different subsets may share the same data qubits, and we want these qubits to be mapped to the same positions in mapimap_{i}. Therefore, after solving the SAT problem for S1,,SiS_{1},\dots,S_{i}, we select the subset SjS_{j} that shares the most data qubits with all data qubits involved in S1SiS_{1}\cup\dots\cup S_{i} as the next SAT problem to solve. Moreover, we add soft constraints in Stage 1 to maximize the number of shared data qubits that remain in their previous positions:

max|{qmapi(q,p)map0i(q,p)}|\max\left|\{q\mid map_{i}(q,p)\vee map_{0\dots i}(q,p)\}\right|

Integrating the ESM circuits. After all ESM circuits for each subset are generated, we connect them to form the complete ESM circuit for the original QEC code. Although the circuits may require different data qubit mappings and ancilla bridge allocations on the architecture, we insert integration layers between them to move the data qubits to meet these varying requirements. Since all ancilla qubits function identically and only data qubits contain the logical information, we only need to route the data qubits instead of all used physical qubits, as general QMR methods do. In the integration layer, to connect ESM circuits, we find the shortest path for each data qubit that changes its position and insert SWAP gates to move it to the new position.

VI IMPLEMENTATION AND EVALUATION

VI-A Experimental Setup

Evaluation setting: Our framework, QECC-Synth, utilizes the state-of-the-art MaxSAT solver, NuWLS-c [52], and the widely-used SAT solver, PySAT [53], with a solving time limit of 7,200 seconds and a memory limit of 128 GB. For logical error analysis, we used Stim [54], a widely-used QEC simulator for ESM circuits, and PyMatching [55], a error syndrome decoder that implements the Minimum Weight Perfect Matching (MWPM) algorithm.

Hardware architectures: We cover a diverse range of practical device architectures in our evaluation. As shown in Fig. 8, the selected architectures are sourced from the latest quantum machines, including Google’s Sycamore [5], IBM’s Osprey, and IBM Q Tokyo [2]. To represent the connectivity of the architecture, we use the average degree of the nodes, denoted as Density(G)=2|Edge|/|Node|Density(G)=2|Edge|/|Node|.

Refer to caption
Figure 8: Overview of device architectures.
TABLE I: Results of QECC-Synth and the baselines for various stabilizer codes across different device architectures.
Code Density Architecture # qubit # Extra CNOT gate Circuit depth
QECC-Synth SATmap Sabre QECC-Synth SATmap Sabre
[[9,1,3]][\![9,1,3]\!] Surface Code 2.82 Square 25 0 0 30 8 17 16
Hexagon 21 14 27* 90 19 34* 35
H-Square 29 24 42* 90 20 49* 21
H-Hexagon 46 56 66* 96 16 47* 26
[[16,4,3]][\![16,4,3]\!] 2D Color Code 4.29 Square 35 20 168* 270 17 132* 56
Hexagon 50 60 Time-Limit 252 18 Time-Limit 47
H-Square 93 72 Time-Limit 468 26 Time-Limit 125
H-Hexagon 115 180* Time-Limit 1,038 30* Time-Limit 324
[[8,3,2]][\![8,3,2]\!] 3D Color Code 3.69 Square 30 0 Not Exist Not Exist 20 Not Exist Not Exist
Hexagon 16 4 Not Exist Not Exist 31 Not Exist Not Exist
H-Square 79 14 Time-Limit 270 30 Time-Limit 40
H-Hexagon 55 38 Time-Limit 228 33 Time-Limit 35
[[7,1,3]][\![7,1,3]\!] Steane Code 3.69 Square 25 0 Not Exist Not Exist 17 Not Exist Not Exist
Hexagon 21 0 Not Exist Not Exist 18 Not Exist Not Exist
H-Square 29 8 Not Exist Not Exist 32 Not Exist Not Exist
H-Hexagon 46 36 Time-Limit 504 30 Time-Limit 112
HGP QLDPC Code 4.00 Square 121 588* Time-Limit 726 70* Time-Limit 205
Hexagon 128 876* Time-Limit 1,236 121* Time-Limit 354
H-Square 176 859* Time-Limit 990 96* Time-Limit 251
H-Hexagon 265 1,275* Time-Limit 1,386 120* Time-Limit 336
[[81,1,9]][\![81,1,9]\!] Surface Code 3.58 Square 289 0 Time-Limit 9,594 8 Time-Limit 2,770
Hexagon 225 6,547* Time-Limit 8,928 391* Time-Limit 2,428
H-Square 251 288 Time-Limit 9,654 15 Time-Limit 2,458
H-Hexagon 387 9,322* Time-Limit 11,064 450* Time-Limit 2,930

Stabilizer codes: Our evaluation covers both classical and recent popular stabilizer codes to demonstrate the generality of our framework. For instance, small-scale [[9,1,3]][\![9,1,3]\!] and large-scale [[81,1,9]][\![81,1,9]\!] surface code are selected to show support for the most popular surface code family. The 2D [[16,4,3]][\![16,4,3]\!] and the 3D [[8,3,2]][\![8,3,2]\!] color codes color codes are included to illustrate the influence of distinct code topologies. The classical [[7,1,3]][\![7,1,3]\!] Steane code is selected for its role as a basic block that can be merged into larger stabilizer codes [21], such as the [[22,4,3]][\![22,4,3]\!] and [[12,2,3]][\![12,2,3]\!] color codes. The HyperGraph Product (HGP) code [38] is chosen to demonstrate our framework’s applicability to recent popular qLDPC codes. Moreover, we adopt some manually designed measurement schemes for specific codes to showcase the extensibility of our framework. Specifically, we adapt Shor’s scheme [56] for the 3D color code and the Steane code to ensure the fault tolerance of the ESM circuits.

To quantify the level of interconnectivity for each stabilizer code, we define the density of a stabilizer code:

Density(C)=2sStabswt(s)|Stabs|+|Data|\displaystyle Density(C)=\frac{2\sum_{s\in Stabs}wt(s)}{\left|Stabs\right|+\left|Data\right|}

Error Model: We follow a widely-used circuit-level error model similar to those in [20, 54, 19], involving the same error rates and types. Specifically, we apply probabilities ranging from 10310^{-3} to 10210^{-2} to the single-qubit depolarizing error channel for single-qubit gates, the two-qubit depolarizing error channel for two-qubit gates, and the Pauli-X error channel for measurement and reset operations. Additionally, for idle errors induced by decoherence, each idle qubit undergoes a single-qubit depolarizing error channel per gate duration with a probability of 2×1042\times 10^{-4} [4, 19, 57]. These errors affect all qubits, including both data and ancilla qubits.

Metrics: We consider two key metrics that significantly impact the fidelity of quantum circuit execution and are widely used to evaluate the performance of general QMR method s [32, 31, 33]. (1) Extra CNOT gate count: We evaluate the extra CNOT gate count required by ESM circuits to compensate for sparse architectures. Previous studies [18, 54] and our experiments in Section VI-D show the high sensitivity of ESM circuits to two-qubit gate errors, making the CNOT gate count a crucial factor that significantly affects the fidelity of logical qubits. (2) Circuit Depth: We assess the Circuit Depth of entire ESM circuit, which is the maximum time coordinates of all gates. Due to the limitation of current quantum computing technology, physical qubits can only function well up to a short ‘lifetime’. Thus, minimizing depth becomes crucial to ensure efficiency. A larger time-step count would introduce more decoherence errors that accumulate, eventually surpassing the fault tolerance threshold of the error correction procedure.

VI-B Compared to Swapping-Based Approaches

We begin by comparing QECC-Synth with two traditional swapping-based approaches designed for the QMR task of general quantum circuits: SATmap (a constraint-based approach) [33] and Sabre (a heuristic approach) [31]. The results in Table I demonstrate that our QECC-Synth consistently synthesizes smaller and faster ESM circuits for stabilizer codes. We highlight the following three results:

(1) Our QECC-Synth shows great improvement even when the code synthesis task is small-scale. For instance, in the case of the [[9,1,3]][\![9,1,3]\!] surface code, QECC-Synth demonstrates an average reduction of 26.5% in the extra CNOT gate count compared to SATmap and 74.9% compared to Sabre. Additionally, the improvement in circuit depth is even more substantial, with an average reduction of 55.5% compared to SATmap and 34.7% compared to Sabre. This highlights the efficiency of QECC-Synth’s bridging-based approach over the traditional swapping-based approach in addressing connectivity disparity problems in ESM circuit synthesis.

(2) The ”*” symbol and ”Time-Limit” entry indicate that the SAT solver times out, returns a sub-optimal result, or does not produce a result. This often occurs when the code becomes complicated and large, such as the HGP qLDPC code, or when the ”code-architecture” gap is substantial, such as mapping the dense [[16,4,3]][\![16,4,3]\!] color code to sparse architectures (Hexagon, Heavy Square, and Heavy Hexagon). This demonstrates that QECC-Synth efficiently prunes the optimization space of ESM circuits by treating and mapping each stabilizer as a whole, rather than mapping each gate in the ESM circuit separately, as traditional QMR approaches do.

(3) The ”Not-Exist” entry indicates that the approach verifies the impossibility of finding a workable code synthesis on a device with the given architecture and a limited number of physical qubits, as the number of physical qubits is always restricted on a practical quantum chiplet [24, 5, 10]. The inability of swapping-based approaches to leverage the flexibility of overlapping ancilla qubits contributes to the occurrence of ”Not-Exist”. These approaches treat data and ancilla qubits as identical, requiring each to be mapped to a distinct physical qubit, which may exceed the available number of physical qubits on the device. For instance, in the case of the [[8,3,2]][\![8,3,2]\!] 3D Color Code and the [[7,1,3]][\![7,1,3]\!] Steane Code, their original ESM circuits apply Shor’s scheme and require more than one ancilla qubit for each stabilizer, resulting in a ”Not-Exist” for the swapping-based approaches.

VI-C Compared to Heuristic Bridging-Based Approach

We compare our QECC-Synth with Surf-Stitch [19], a heuristic method that can only work on the surface code and specific regular architectures. In Table II, we show the synthesis results of the d=5d=5 surface code on both perfect and defective architectures [42, 43, 44] that have a faulty qubit in the middle due to fabrication defects. The result shows that QECC-Synth has a wider range of applicability while achieving equal or better ESM circuits than Surf-Stitch. We highlight the following three results:

TABLE II: Detailed information about synthesized distance-5 surface codes on perfect or defective architectures.
Architecture Metric QECC-Synth Surf-Stitch
# Extra CNOT gate  Circuit depth # Extra CNOT gate  Circuit depth
Square Perfect 0 8 0 8
Defective 12 17 ×\times ×\times
Hexagon Perfect 72 20 120 26
Defective 76 17 ×\times ×\times
Heavy Square Perfect 80 15 80 24
Defective 94 20 ×\times ×\times
Heavy Hexagon Perfect 216 18 224 40
Defective 216 23 ×\times ×\times

(1) Although at most cases of perfect architectures, the improvement on CNOT gates number by QECC-Synth  is marginal, as the Surf-Stitch’s mannual mapping of surface code is already near optimal, QECC-Synth still find a synthesis on hexagon with using 40% less extra CNOT gates. Moreover, due to our more concurrent scheduling strategy, QECC-Synth achieves a average reduction of 38.5% in circuit depth.

(2) In the presence of faulty physical qubits that cannot be used in ESM circuits due to fabrication defects [42, 58, 43], Surf-Stitch fails to operate because the architecture is no longer regular. However, our QECC-Synth adapts seamlessly to these defective architectures with only a minor increase in CNOT gates and circuit depth.

Refer to caption
Figure 9: Logical error rate of distance-5 surface codes synthesized by QECC-Synth and Surf-Stitch on heavy-square architecture. The error threshold is the physical error rate at which the code curves of different distances intersect, which is represented with red dotted lines.

(3) For two synthesized ESM circuits with an equal count of CNOT gates (e.g. perfect heavy-square), circuit depth significantly affects their error correction capability. As shown in Fig. 9, we simulated the logical error rates for surface codes of different distances on the heavy-square architecture, each using 10610^{6} slots of simulation. The results for QECC-Synth consistently show significantly lower logical error rates, ranging from 6.8x to 8.6x lower for the distance-7 surface code, despite both approaches using the same number of CNOT gates. Moreover, surface codes synthesized by QECC-Synth also show an improved error threshold. Although the improvement from 0.53% to 0.60% may seem marginal, it significantly affects the scalability of surface codes. For instance, if we aim to implement a logical qubit on a device with a physical error rate of 0.50%, Surf-Stitch would require 10x more physical qubits to achieve the same logical error rate.

VI-D Ablation Study

To justify prioritizing ”# extra CNOT gates” over ”circuit depth” as the primary optimization goal and employing a two-stage SAT approach to optimize them separately, we perform a breakdown analysis of the logical error rate to identify the most critical factor for the fidelity of the ESM circuit. Additionally, we conduct a scalability analysis to demonstrate the performance of our heuristic relaxation method.

Breakdown analysis of logical error rate. This study provides a breakdown analysis of how the error threshold shifts across two vital error types: two-qubit CNOT gate errors and device idle errors. The simulation focuses on surface codes on 2-D grid hardware, but the conclusion can be readily extrapolated to broader contexts. This analysis provides additional support for the rationale behind prioritizing the reduction of # CNOT gates (linked to accumulated CNOT errors) over circuit depth (linked to accumulated idle errors) when optimizing QEC code synthesis.

Refer to caption
Figure 10: Breakdown analysis of the influence of CNOT gate errors and idle errors on the logical error rate.

We conducted 10610^{6} simulation slots for each logical error point. When analyzing the CNOT gate error, the idle error is set to 0, and vice versa. As shown in Fig. 10, pure CNOT gate error exhibits a per-step error threshold of 1.2%, while pure idle error demonstrates a threshold of 5%. The significantly lower threshold for CNOT errors highlights both the reduced tolerance for this type of error and its amplified impact on the overall logical error rate. This emphasizes the importance of prioritizing the reduction of the CNOT gate count.

Scalability Analysis. In this study, we evaluate the scalability of QECC-Synth in comparison to the solver-based SATmap and test our relaxation method by code partition on dense and large-scale stabilizer codes.

TABLE III: Size of MaxSAT-encoded problem for [[9,1,3]][\![9,1,3]\!] surface code synthesis by QECC-Synth and SATmap
Metrics Arch Square Hexagon Heavy Square Heavy Hexagon
# Variable QECC-Synth 6.38×1036.38\times 10^{3} 1.24×1041.24\times 10^{4} 2.27×1042.27\times 10^{4} 1.07×1051.07\times 10^{5}
SATmap 5.52×1045.52\times 10^{4} 4.04×1044.04\times 10^{4} 7.24×1047.24\times 10^{4} 1.71×1051.71\times 10^{5}
# Hard clause QECC-Synth 1.51×1041.51\times 10^{4} 2.64×1042.64\times 10^{4} 4.76×1044.76\times 10^{4} 2.18×1052.18\times 10^{5}
SATmap 1.80×1061.80\times 10^{6} 9.98×1059.98\times 10^{5} 1.83×1061.83\times 10^{6} 4.22×1064.22\times 10^{6}
# Soft clause QECC-Synth 228228 196196 260260 396396
SATmap 14,40014,400 10,08010,080 19,48819,488 49,68049,680

The sizes of the MaxSAT-encoded problem are shown in Table III. It reveals that tasks from SATmap exhibit 1.5x to 8.5x more variables, 20x to 120x more hard constraints, and 50x to 125x more soft constraints than the tasks from QECC-Synth. This indicates that our QECC-Synth method offers a more efficient approach to encoding the QEC code mapping problem than SATmap, by formalizing the special structure characteristic of the measurement circuit in stabilizers.

Moreover, the synthesis results of the HGP qLDPC code and the d=9d=9 surface code in Table I further demonstrate the efficiency of QECC-Synth on dense and large-scale stabilizer codes using the heuristic relaxation method. It shows significant improvements in reducing extra CNOT gates and circuit depth compared to traditional swapping-based approaches.

VII Related Work

Swapping-based methods. Extensive research has addressed the challenge of mapping general quantum circuits onto hardware with limited connectivity. These methods typically fall into one of three categories: constraint-based [59, 60, 61, 33], heuristic [31, 62, 63], or a hybrid approach [64]. However, these techniques are inadequate for ESM circuits due to the inserted SWAP gates, which disrupt qubit locations and hinder parallel execution of stabilizer measurements with shared data qubits. Moreover, introducing SWAP gates can elevate the circuit’s error rate, compromising the precision needed for effective ESM circuits.

Bridging-based methods. The original bridging-based methods [21, 35, 65, 66, 37] extend single ancilla qubits into ancilla bridges to alleviate the connectivity constraint. This approach offers fixed qubit locations and introduces fewer additional gates compared to swap-based methods, enhancing performance. However, these methods are designed for single ESM circuits and struggle with complex dependencies among stabilizer measurements within QEC codes. Recent efforts have applied bridging-based techniques to entire QEC codes [67, 20, 19], but they are limited to specific QEC codes and hardware architectures, lacking adaptability to broader settings. Furthermore, these approaches rely on heuristic design without optimality guarantees.

VIII Conclusion

This paper introduces the first automated compilation framework for implementing ESM circuits using the bridging method. Our approach demonstrates broad applicability across diverse QEC codes and hardware architectures, including systems with defective qubits. By systematically classifying and leveraging the primary flexibilities of the bridging method, we effectively explore its extensive design space and formalize ESM circuit implementation as a two-stage MaxSAT problem solved by high-performance SAT solvers. Comparative evaluations show our method significantly outperforms existing swap-based and bridging approaches while achieving superior adaptability. These advancements represent a significant step toward realizing long-term fault-tolerant quantum computing goals.

IX Acknowledgments

We thank the anonymous reviewers for their valuable and constructive feedback. This work was supported in part by NSF 2138437, NSF 2048144, and the Robert N. Noyce Trust. This material is based upon work supported by the U.S. Department of Energy, Office of Science, National Quantum Information Science Research Centers, Quantum Science Center.

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