Resource-Efficient Quantum Computing
by Breaking Abstractions

Since the early days of quantum computing, quantum compilation has been recognized as one of the central tasks in realizing practical quantum computation. Quantum compilation was first defined as the problem of synthesizing quantum circuits for a given unitary matrix. The celebrated Solovay-Kitaev theorem [30] states that such synthesis is always possible if a universal set of quantum gates is given. Now the term of quantum compilation is used more broadly and almost all stages in Fig. 1 can be viewed as part of the quantum compilation process.

There are many indications that current quantum compilation stack (Fig. 1) is highly-inefficient. First, current circuit synthesis algorithms are far from saturating (or being closed to) the asymptotic lower bound in the general case [49, 30]. Also, the formulated circuit synthesis problem is based on the fundamental abstraction of quantum ISA (Section II-B) and largely discussed in a hardware-agnostic settings in previous work but the underlying physical operations cannot be directly described by the logical level ISA (as shown in Fig. 2). The translation from the logical ISA to the operations directly supported by the hardware is typically done in an ad-hoc way. Thus, there is a mismatch between the expressive logical gates and the set of instructions that can be efficiently implemented on a real system. This mismatch significantly limits the efficiency of the current quantum computing stack thus the underlying quantum devices’ computing ability and wastes precious quantum coherence. While improving the computing efficiency is always valuable, improving quantum computing efficiency is do-or-die: computation has to finish before qubit decoherence or the results will be worthless. Thus, improving the compilation process is one of the most, if not the most, crucial goals in near-term QC system design.

By identifying this mismatch and the fundamental limitation in the ISA abstraction, in [129, 148], we proposed a quantum compilation technique that optimizes across existing abstraction barriers to greatly reduce latency while still being practical for large numbers of qubits. Specifically, rather than limiting the compiler to use 1- and 2-qubit quantum instructions, our framework aggregates the instructions in the logical ISA into a customized set of instructions that correspond to optimized control pulses. We compare our methodology to the standard compilation workflow on several promising NISQ quantum applications and conclude that our compilation methodology has an average speedup of $5\times$ with a maximum speedup of $10\times$. We use the rest of this section to introduce this compilation methodology, starting with defining some basic concepts.

In the quantum computing stack, a restricted set of 1- and 2-qubit quantum instructions are provided for describing the high-level quantum algorithms, analogous to the Instruction Set Architecture (ISA) abstraction in classical computing. In this paper, we call this instruction set the logical ISA. The 1-qubit gates in the logical ISA include the Pauli gates, $P=\{X,Y,Z\}$. It also includes the Hadamard $H$ gate, whose symbol in the circuit model is given as an example in Fig. 2 on the left column. The typical 2-qubit instruction in the logical instruction set is the Controlled-NOT (CNOT) gate, which flips the state of the target qubit based on the state of the control qubit.

However, usually quantum computing devices does not directly support the logical ISA. Based on the system characteristics, we can define the physical ISA that can be directly mapped to the underlying control signals. For example, superconducting devices typically has Cross-Resonance (CR) gate or $i$SWAP gate as their intrinsic 2-qubit instruction, whereas for trapped-ion devices the intrinsic 2-qubit instruction can be the Mølmer–Sørensen gate or the controlled phase gate.

As shown in Fig. 2 and discussed in the last subsection, underlying physical operations in the hardware such as microwave control pulses and modulated laser beam are abstracted as quantum instructions. A quantum instruction are simply as pre-fined control pulse sequences.

The underlying evolution of the quantum system is continuous and so are the control signals. The continuous control signals offer much richer and flexible controllability than the quantum ISA. The control pulses can drive the quantum computing hardware to a desired quantum states by varying a system-dependent and time-dependent quantity called the Hamiltonian. The Hamiltonian of a system determines the evolution path of the quantum states. The ability to engineer real-time system Hamiltonian allows us to navigate the quantum system to the quantum state of interest through generating accurate control signals. Thus, quantum computation can be done by constructing a quantum system in which the system Hamiltonian evolves in a way that aligns with a quantum computing task, producing the computational result with high probability upon final measurement of the qubits. In general, the path to a final quantum state is not unique and finding the optimal evolution path is a very important but challenging problem [115, 116, 117].

Being hardware-agnostic, the quantum operation sequences composed by logical ISA have limited freedom in terms of controllability and usually will not be mapped to the optimal evolution path of the underlying quantum system, thus there is a mismatch between the ISA and low-level quantum control. With two simple examples, we demonstrate this mismatch.

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  We can consider the instruction sequence consists of a CNOT gate followed by a $X$ gate on the control bit. In current compilation workflow, these two logical gates will be further decomposed into the physical ISA and be executed sequentially. However, on SC QIP platforms, the microwave pulses that implement these two instructions could in fact be applied simultaneously (because of their commutativity). Even the commutativity can be captured by the ISA abstraction, in the current compilation workflow, the compiled control signals are sub-optimal.

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  SWAP gate is an important quantum instruction for circuit mapping. The SWAP operation is usually decomposed as 3 Controlled-NOT (CNOT) operations, as realized in the circuit below. This decomposition could be thought of the implementation of in-place memory SWAPs with three alternating XORs for classical computation. However, for systems like quantum dots [114], the SWAP operation is directly supported by applying particular constant control signals for a certain period of time. In this case, this decomposition of SWAP into three CNOTs introduces substantial overhead.

  

In experimental physics settings, equivalences from simple gate sequences to control pulses can be hand optimized [113]. However, when circuits become larger and more complicated, this kind of hand optimization become less efficient and the standard decomposition becomes less favorable, motivating a shift toward numerical optimization methods that are not limited by the ISA abstraction.

Quantum Optimal Control (QOC) theory provides an alternative in terms of finding the optimal evolution path for the quantum compilation tasks. Quantum optimal control algorithms typically perform analytical or numerical methods for this optimization, among which, gradient ascent methods, such as the GRadient Ascent Pulse Engineering (GRAPE) [119, 120] algorithm, are widely used. The basic idea of GRAPE is as follows: for optimizing the control signals of $M$ parameters ($u_{1},\ldots,u_{M}$) for a target quantum state, in every iteration, GRAPE minimizes the deviation of the system evolution by calculating the gradient of the final fidelity with respect to the $M$ control parameters in the $M$ dimensional space. Then GRAPE will update the paramters in the direction of the gradient with adaptive step size [119, 120, 115]. With a large number of iterations, the optimized control signals are expected to converge and find optimized pulses.

In [129], we utilize GRAPE to optimize our aggregated instructions that are customized for each quantum circuit as opposed to selecting instructions from a pre-defined pulse sequences. However, one disadvantage of numerical methods like GRAPE is that the running time and memory use grow exponentially with the size of the quantum system for optimization. In our work, we are able to use GRAPE for optimizing quantum systems of up to  10 qubits with the GPU accelerated optimal control unit [115]. As shown in our result, the limit of 10 qubits does not put restrictions on the result of our compilation methodology.

Next, we will illustrate the workflow of our compilation methodology with a circuit instance of the Quantum Approximate Optimization Algorithm (QAOA) for solving the MAXCUT problem on the triangle graph (Fig. 3). ¹¹1The angle parameters $\gamma$ and $\beta$ can be determined by variational methods [122] and are set to $5.67$ and $1.26$. This QAOA circuit with logical ISA (or variants of it up to single qubit gates) can be reproduced by most existing quantum compilers. This instance of the QAOA circuit is generated by the ScaffCC compiler, as shown in Fig. 3 (a). We assume this circuit is executed on a superconducting architecture with 1D nearest neighbor qubit connectivity. A SWAP instruction is inserted in the circuit to satisfy the linear qubit connectivity constraints.

On the other hand, our compiler generates the aggregated instruction set $G_{1}-G_{5}$ as illustrated in Fig. 3 (b) automatically, and uses GRAPE to produce highly-optimized pulse sequences for each aggregated instruction. In this minimal circuit instance, our compilation method reduces the total execution time of the circuit by about $2.97\times$ comparing to compilation with restricted ISA. Fig. 3 (c) and (d) show the generated pulses for $G_{3}$ with ISA-based compilation and with our aggregated instruction based, pulse-level optimized compilation.

Now we give a systematic view of the workflow of our compiler. First, at the program level, our compiler performs module flattening and loop unrolling to produce the quantum assembly (QASM), which represents a schedule of the logical operations. Next, the compiler enters the commutativity detection phase. Different from the ISA-based approach, in this phase, our compilation process converts the QASM code to a more flexible logical schedule that explores the commutativity between instructions. To further explore the commutativity in the schedule, the compiler aggregates instructions in the schedule to produce a new logical schedule with instructions that represents diagonal matrices (and are of high commutativity). Then the compiler enters the scheduling and mapping phase. Because of commutativity awareness, our compiler can generate a much more efficient logical schedule by re-arranging the aggregated instructions with high commutativity. The logical schedule is then converted to a physical schedule after the qubit mapping stage. Then the compiler generates the final aggregated instructions for pulse optimization and use GRAPE for producing the corresponding control pulses. The goal of the final aggregation is to find the optimal instruction set that produces the lowest-latency control pulses while preserving the parallelism in the circuit aggregations that are small as much as possible. Finally, our compiler outputs an optimized physical schedule along with the corresponding optimized control pulses. Fig. 4 shows the Gate Dependency Graph (GDG) of the QAOA circuit in Figure 5 in different compilation stages. Next, we walk through the compilation backend with this example, starting from the commutativity detection phase.

In [129], we selected 9 important quantum /classical-quantum hybrid algorithms in the NISQ era as our benchmarks. Across all 9 benchmarks, our compilation scheme achieves a geometric mean of 5.07× pulse time reduction comparing to the standard gate-based compilation. The result in [129] indicates that addressing the mismatch between quantum gates and the control pulses by breaking the ISA abstraction can greatly improve the compilation efficiency. Going beyond the ISA-based compilation, this work opens up a door to new QC system designs.

QC systems have spatial and temporal variations in noise due to manufacturing imperfections, imprecise qubit control and external interference. To motivate the necessity for breaking the ISA abstraction barrier, we present real-system statistics of hardware noise in systems from three leading QC vendors – IBM, Rigetti and University of Maryland. IBM and Rigetti systems use superconducting qubits [9, 10] and University of Maryland (UMD) uses trapped ion qubits [11]. The gates in these systems are periodically calibrated and their error rates are measured.

Figure 6 shows the coherence times and two-qubit gate error rates in IBM’s 16-qubit system (IBMQ16 Rueschlikon). From daily calibration logs we find that, the average qubit coherence time is 40 microseconds, two-qubit gate error rate is 7%, readout error rate is 4% and single qubit error rate is 0.2%. The two-qubit and readout errors are the dominant noise sources and vary up to 9X across gates and calibration cycles. Rigetti’s systems also exhibit error rates and variations of comparable magnitude. These noise variations in superconducting systems emerge from material defects due to lithographic manufacturing, and are expected in future systems also [7, 8].

Trapped ion systems also have noise fluctuations even though the individual qubits are identical and defect-free. On a 5-qubit trapped ion system from UMD, we observed up to $3$x variation in the two-qubit gate error rates because of fundamental challenges in qubit control using lasers and their sensitivity to motional mode drifts from temperature fluctuations.

We found that these microarchitectural noise variations dramatically influence program correctness. When a program is executed on a noisy QC system, the results may be corrupted by gate errors, decoherence or readout errors on the hardware qubits used for execution. Therefore, it is crucial to select the most reliable hardware qubits to improve the success rate of the program (the likelihood of correct execution). The success rate is determined by executing a program multiple times and measuring the fraction of runs that produce the correct output. High success rate is important to ensure that the program execution is not dominated by noise.

Our work breaks the ISA abstraction barrier by developing compiler optimizations which use hardware calibration data. These optimizations boost the success rate a program run by avoiding portions of the machine with poor coherence time and operational error rates.

We first review the key components in a QC compiler. The input to the compiler is a high-level language program (Scaffold in our framework) and the output is machine executable assembly code. First, the compiler converts the program to an intermediate repreesentation (IR) composed of single and two-qubit gates by decomposing high-level QC operations, unrolling all loops and inlining all functions. Figure 7a shows an example IR. The qubits in the IR (program qubits) are mapped to distinct qubits in the hardware, typically in a way that reduces qubit communication. Next, gates are scheduled while respecting data dependencies. Finally, on hardware with limited connectivity, such as superconducting systems, the compiler inserts SWAP operations to enable 2-qubit operations between non-adjacent qubits.

Figure 7b and 7c show two compiler mappings for a 4-qubit program on IBM’s 16-qubit system. In the first mapping, the compiler must insert SWAPs to perform the two-qubit gate between $p_{1}$ and $p_{3}$. Since SWAP operations are composed of three two-qubit gates, they are highly error prone. In contrast, the second mapping requires no SWAPs because the qubits required for the CNOTs are adjacent. While SWAP optimizations can be performed using the device ISA, the second mapping is also noise-optimized i.e., it uses qubits with high coherence time and low operational error rates. By considering microarchitectural noise characteristics, our compiler can determine such noise-optimized mappings to improve the program success rate.

We developed three strategies for noise optimization. First, our compiler maps program qubits onto hardware locations with high reliability, based on the noise data. We choose the initial mapping based on two-qubit and readout error rates because they are the dominant sources of error. Second, to mitigate decoherence errors, all gates are scheduled to finish before the coherence time of the hardware qubits. Third, our compiler optimizes the reliability of SWAP operations by minimizing the number of SWAPs whenever possible and performing SWAPs along reliable hardware paths.

Our compiler implements the above strategies by finding the solution to a constrained optimization problem using a Satisfiability Modulo Theory (SMT) solver. The variables and constraints in the optimization encode program information, device topology constraints and noise information. The variables express the choices for program qubit mappings, gate start times and routing paths. The constraints specify that qubit mappings should be distinct, the schedule should respect program dependencies and that routing paths should be non-overlapping. Fig. 8 summarizes the optimization-based compilation pipeline for IBMQ16.

The objective of our optimization is to maximize the success rate of a program execution. Since the success rate can only be determined from a real-system run, we model it at compile time as the program reliablity. We define the reliability of a program as the product of the reliability of all gates in the program. Although this is not a perfect model for the success rate, it serves as a useful measure of overall correctness [140, 6]. For a given mapping, the solver determines the reliability of each two-qubit and readout operation and computes an overall reliability score. The solver maximizes the reliability score over all mappings by tracking and adapting to the error rates, coherence limits, and qubit movement based on program qubit locations.

In practice, we use the Z3 SMT solver to express and solve this optimization. Since the reliability objective is a non-linear product, we linearize the objective by optimizing for the additive logarithms of the reliability scores of each gate. We term this algorithm as R-SMT^★. The output of the SMT solver is used to create machine executable code in the vendor-specified assembly language.

We present real-system evaluation on IBMQ16. Our evaluation uses 12 common QC benchmarks, compiled using R-SMT^★and T-SMT^★ which are variants of our compiler and IBM’s Qiskit compiler (version 0.5.7) [5] which is the default for this system. R-SMT^★ optimizes the reliability of the program using hardware noise data. T-SMT^★ optimizes the execution time of the program considering real-system gate durations and coherence times, but not operational error rates. IBM Qiskit is also noise-unaware and uses randomized algorithms for SWAP optimization. For each benchmark and compiler, we measured the success rate on IBMQ16 system using 8192 trials per program. Success rate of 1 indicates a perfect noise-free execution.

Figure 10 shows the success rate for the three compilers on all the benchmarks. R-SMT^★ has higher success rate than both baselines on all benchmarks, demonstrating the effectiveness of noise-adaptive compilation. Across benchmarks R-SMT^★ obtains geomean $2.9$x improvement over Qiskit, with up to $18$x gain. Figure 9 shows the mapping used by Qiskit, T-SMT^★and R-SMT^★for BV4. Qiskit places qubits in a lexicographic order without considering CNOT and readout errors and incurs extra swap operations. Similarly, T-SMT^★is also unaware of noise variations across the device, resulting in mappings which use unreliable hardware. R-SMT^★outperforms these baselines because it maximizes the likelihood of reliable execution by leveraging microarchitectural noise characteristics during compilation.

Full results of our evaluation on 7 QC systems from IBM, Rigetti and UMD can be found in [12, 13].

Our work represents one of the first efforts to exploit hardware noise characteristics during compilation. We developed optimal and heuristic techniques for noise adaptivity and performed comprehensive evaluations on several real QC systems [13]. We also developed techniques to mitigate crosstalk, another major source of errors in QC systems, using compiler techniques that schedule programs using crosstalk characterization data from the hardware [89]. In addition, our techniques are already being used in industry toolflows [20, 19]. Recognizing the importance of efficient compilation, other research groups have also recently developed mapping and routing heuristics [3, 4] and techniques to handle noise [2, 1].

Our noise-adaptivity optimizations offer large gains in success rate. These gains mean the difference between executions which yield correct and usable results and executions where the results are dominated by noise. These improvements are also multiplicative against benefits obtained elsewhere in the stack and will be instrumental in closing the gap between near-term QC algorithms and hardware. Our work also indicates that it is important to accurately characterize hardware and expose characterization data to software instead of hiding it behind a device-independent ISA layer. Additionally our work also proposes that QC programs should be compiled once-per-execution using the latest hardware characterization data to obtain the best executions.

Going beyond noise characteristics, we also studied the importance of exposing other microarchitectural information to software. We found that when the compiler has access to the native gates available in the hardware (micro operations used to implement ISA-level gates), it can further optimize programs and improve success rates. Overall, our work indicates that QC machines are not yet ready for technology independent abstractions that shield the software from hardware. Bridging the information gap between software and hardware by breaking abstraction barriers will be increasingly important on the path towards practically useful NISQ devices.

We develop the intuition for how qutrits can be useful by considering the example of constructing an AND gate. In the framework of quantum computing, which requires reversibility, AND is not permitted directly. For example, consider the output of 0 from an AND gate with two inputs. With only this information about the output, the value of the inputs cannot be uniquely determined (00, 01, and 10 all yield an AND output of 0). However, these operations can be made reversible by the addition of an extra, temporary workspace bit initialized to 0. Using a single additional such ancilla, the AND operation can be computed reversibly as in Figure 11. While this approach works, it is expensive—in order to decompose the Toffoli gate in Figure 11 into hardware-implementable one- and two- input gates, it is decomposed into at least six CNOT (controlled-NOT) gates.

However, if we break the qubit abstraction and allow occupation of a higher qutrit energy level, the cost of the Toffoli AND operation is greatly diminished. Before proceeding, we review the basics of qutrits, which have three computational basis states: $\ket{0}$, $\ket{1}$, and $\ket{2}$. A qutrit state $\ket{\psi}$ may be represented analogously to a qubit as $\ket{\psi}=\alpha\ket{0}+\beta\ket{1}+\gamma\ket{2}$, where $\norm{\alpha}^{2}+\norm{\beta}^{2}+\norm{\gamma}^{2}=1$. Qutrits are manipulated in a similar manner to qubits; however, there are additional gates which may be performed on qutrits. We focus on the $X_{+1}$ and $X_{-1}$ operations, which are addition and subtraction gates, modulo 3. For example $X_{+1}$ elevates $\ket{0}$ to $\ket{1}$ and elevates $\ket{1}$ to $\ket{2}$, while wrapping $\ket{2}$ to $\ket{0}$.

Just as single-qubit gates have qutrit analogs, the same holds for two-qutrit gates. For example, consider the CNOT operation, where an X gate is performed conditioned on the control being in the $\ket{1}$ state. For qutrits, an $X_{+1}$ or $X_{-1}$ gate may be performed, conditioned on the control being in any of the three possible basis states. Just as qubit gates are extended to take multiple controls, qutrit gates are extended similarly.

In Figure 12, a Toffoli decomposition using qutrits is given. A similar construction for the Toffoli gate is known from past work [95, 96]. The goal is to perform an X operation on the last (target) input qubit $q_{2}$ if and only if the two control qubits, $q_{0}$ and $q_{1}$, are both $\ket{1}$. First a $\ket{1}$-controlled $X_{+1}$ is performed on $q_{0}$ and $q_{1}$. This elevates $q_{1}$ to $\ket{2}$ iff $q_{0}$ and $q_{1}$ were both $\ket{1}$. Then a $\ket{2}$-controlled $X$ gate is applied to $q_{2}$. Therefore, $X$ is performed only when both $q_{0}$ and $q_{1}$ were $\ket{1}$, as desired. The controls are restored to their original states by a $\ket{1}$-controlled $X_{-1}$ gate, which undoes the effect of the first gate. The key intuition in this decomposition is that the qutrit $\ket{2}$ state can be used instead of ancilla to store temporary information.

The intuition of our technique extends to more complicated gates. In particular, we consider the Generalized Toffoli gate, a ubiquitous quantum operation which extends the Toffoli gate to have any number of control inputs. The target input is flipped if and only if all of the controls are activated. Our qutrit-based circuit decomposition for the Generalized Toffoli gate is presented in Figure 13. The decomposition is expressed in terms of three-qutrit gates (two controls, one target) instead of single- and two- qutrit gates, because the circuit can be understood purely classically at this granularity. In actual implementation and in our simulation, we used a decomposition [77] that requires 6 two-qutrit and 7 single-qutrit physically implementable quantum gates.

Our circuit decomposition is most intuitively understood by treating the left half of the the circuit as a tree. The desired property is that the root of the tree, $q_{7}$, is $\ket{2}$ if and only if each of the 15 controls was originally in the $\ket{1}$ state. To verify this property, we observe the root $q_{7}$ can only become $\ket{2}$ iff $q_{7}$ was originally $\ket{1}$ and $q_{3}$ and $q_{11}$ were both previously $\ket{2}$. At the next level of the tree, we see $q_{3}$ could have only been $\ket{2}$ if $q_{3}$ was originally $\ket{1}$ and both $q_{1}$ and $q_{5}$ were previously $\ket{2}$, and similarly for the other triplets. At the bottom level of the tree, the triplets are controlled on the $\ket{1}$ state, which are only activated when the even-index controls are all $\ket{1}$. Thus, if any of the controls were not $\ket{1}$, the $\ket{2}$ states would fail to propagate to the root of the tree. The right half of the circuit performs uncomputation to restore the controls to their original state.

After each subsequent level of the tree structure, the number of qubits under consideration is reduced by a factor of $\sim 2$. Thus, the circuit depth is logarithmic in $N$, which is exponentially smaller than ancilla-free qubit-only circuits. Moreover, each qutrit is operated on by a constant number of gates, so the total number of gates is linear in $N$.

We verified our circuits, both formally and via simulation. Our verification scripts are available on our GitHub [74].

Table I shows the scaling of circuit depths and two-qudit gate counts for all three benchmarked circuits. The QUBIT-based circuit constructions from past work are linear in depth and have a high linearity constant. Augmenting with a single borrowed ancilla (QUBIT+ANCILLA) reduces the circuit depth by a factor of 8. However, both circuit constructions are significantly outperformed by our QUTRIT construction, which scales logarithmically in $N$ and has a relatively small leading coefficient. While there is not an asymptotic scaling advantage for two-qudit gate count, the linearity constant for our QUTRIT circuit is 70x smaller than for the equivalent ancilla-free QUBIT circuit.

We ran simulations under realistic superconducting and trapped ion device noise. The simulations were run in parallel on over 100 n1-standard-4 Google Cloud instances. These simulations represent over 20,000 CPU hours, which was sufficient to estimate mean fidelity to an error of $2\sigma<0.1\%$ for each circuit-noise model pair.

The full results of our circuit simulations are shown in Figure 14. All simulations are for the 14-input (13 controls, 1 target) Generalized Toffoli gate. We simulated each of the three circuit benchmarks against each of our noise models (when applicable), yielding the 16 bars in the figure. Notice that our qutrit circuit consistently outperforms qubit circuits, with advantages ranging from 2x to 10,000x.

The results presented in our work in [37, 38] are applicable to quantum computing in the near term, on machines that are expected within the next five years. By breaking the qubit abstraction barrier, we extend the frontier of what is computable by quantum hardware right now, without needing to wait for better hardware. As verified by our open-source circuit simulator coupled with realistic noise models, our circuits are more reliable than qubit-only equivalents, suggesting that qutrits offer a promising path towards scaling quantum computers. We propose further investigation into what advantage qutrits or qudits may confer. More broadly, it is critical for quantum architects to bear in mind that standard abstractions in classical computing do not necessarily transfer to quantum computation. Often, this presents unrealized opportunities, as in the case of qutrits.

We describe the GKP qubits in the phase space. For a comparison, we first discuss the phase space diagram for a classical harmonic oscillator and a superconducting qubit.

Classical Harmonic Oscillators Examples of Classical Harmonic Oscillators (CHO) include LC circuits, springs and pendulums with small displacement. The voltage/displacement (denoted as $p$) and the current/momentum (denoted as $q$) value completely characterize the dynamics of CHO systems. The phase space diagram plots $p$ vs $q$, which for CHOs are circles (up to normalization) with the radius representing the system energy. The energy of CHOs can be any non-negative real value.

Quantum Harmonic Oscillators The Quantum Harmonic Oscillator is the quantized verision of the CHO and is the physical model for superconducting LC circuits and superconducting cavity modes. One of the values get quantized for QHOs is the system energy, which can only take equally-spaced non-zero discrete values. The lowest allowed energy is not 0 but $\frac{1}{2}$ (up to normalization). We call the quantum state with the lowest energy the ground state. For a motion with a certain energy, the phase space diagram is not a circle anymore but a quasi-distribution that can be described by the Wigner function. We say the distribution is a “quasi" distribution because the probability can be negative. The phase space diagram for the ground state and first excited state is plot in Fig. 15.

Superconducting Charge Qubits The QHO does not allow us selectively address the energy levels, thus leakage errors will occur if we use the lowest two levels as the qubit logic space. For example, a control signal that provides the energy difference $\Delta E$ enables the transition $\ket{0}\rightarrow\ket{1}$, but will also make the transition $\ket{1}\rightarrow\ket{2}$ which brings the state out of the logic space. To avoid this problem, the Cooper Pair Box (CPB) design of a superconducting charge qubit replaces the inductor (see Fig. 17) with a Josephson junction, making the circuit an anharmonic oscillator, in which the energy levels are not equally spaced anymore. The Wigner function for CPB eigenstates are visually similar to those of QHO and only differ from them to the first order of the anharmonicity, thus we do not plot them in Fig. 15 separately.

We hope that with utilizing the whole physical states (higher energy levels), we can use the redundant space to encode and extract error information. However, the Heisenberg uncertainty principle sets the fundamental limit on what error information we can extract from the physical states — the more we know about the $q$ variable, the less we know about the $p$ variable. For example, we can “squeeze" the ground state of the QHO (also known as the vacuum state) in the $p$ direction, however, the distribution in the $q$ direction spreads, as shown in Fig. 18. Usually, we have to know both the $p$ and $q$ value to characterize the error information unless we know the error is biased. Thus, it’s a great challenge to design encodings in the phase space to reveal error information.

The GKP states are also called the grid states because each of them is a rectangular lattice in the phase space (see Fig. 15). There are also other types of lattice in the GKP family, for example, the hexagonal GKP [24]. Intuitively, the GKP encoding “breaks" the Heisenberg uncertainty principle—we do not know what are the measured $p$ and $q$ values of the state (thus expected values of $p$ and $q$ remain uncertain), but we do know that they must be integer multiples of the spacing of the grid. Thus, we have access to the error information in both directions and if we measure values that are not multiples of the spacing of the grid, we know there must be errors. Formally, the ideal GKP logical states are given by,

where $S_{p}=e^{-2i\sqrt{\pi}p}$ is the displacement operator in $q$ space, which shift a wave function in the $q$ direction by 2$\sqrt{\pi}$. These definitions show that for GKP logical 0 and 1, the spacing of the grid in $q$ direction is $2\sqrt{\pi}$ and the spacing in the $p$ is $\sqrt{\pi}$. In $q$ direction, the logical $\ket{0}$ state has peaks at even multiples of $\sqrt{\pi}$ and the logical $\ket{1}$ state has peaks at odd multiples of $\sqrt{\pi}$. For logical $\ket{+}$ and $\ket{-}$, the spacing in $p$ and $q$ grid s are switched.

Approximate GKP states The ideal GKP states require infinite energy thus are not realistic. In the lab, we can prepare approximate GKP states as illustrated in Fig. 19, where peaks and the envelope are Gaussian curve.

Error correction with GKP qubits GKP qubits are designed to correct shift errors in $q$ and $p$ axis. A simple decoding strategy will be shifting the GKP state back to the closest peak. For example, if we measure a $q$ value to be $2\sqrt{\pi}+\Delta q$, where $\Delta q<\frac{\sqrt{\pi}}{2}$, then we can shift it back to $2\sqrt{\pi}$. With this simple decoding, GKP can correct all shift errors smaller than $\frac{\sqrt{\pi}}{2}$. While there are other proposals for encoding qubits in QHO [32, 29, 33] that are designed for realistic errors such as photon loss, it is shown that GKP qubits have the most error correcting ability in the regime of experimental relevance [28].

In addition, GKP qubits can also provide error correction information when concatenating with Quantum Error Correction Codes (QECC) and yield higher thresholds. For example, when combing the GKP qubits with a surface code, the measured continuous $p$ and $q$ value in the stabilizer measurement can reveal more about the error distribution than traditional qubits [34, 35, 36].

Lastly, it has been shown that given a supply of GKP-encoded Pauli eigenstates, universal fault-tolerant quantum computation can be achieved using only Gaussian operations [132]. Comparing to qubit error correction codes, the GKP encoding enables much simpler fault-tolerant constructions.

The GKP encoding has straightforward logical operation and promising error correcting performance. However, the difficulty of using GKP qubits in QIP platforms lies in its preparation since they live in highly non-classical states with relatively high mean photon number ($i.e.,$ the average energy levels). Thus, realiable preparation of encoded GKP states is an important problem. In [133], we gave fault-tolerance definitions for GKP preparation in superconducting cavities and designed a protocol that fault-tolerantly prepares the GKP states. We briefly describe the main ideas.

The GKP qubit architecture is a promising candidate for both near-term and fault-tolerant quantum computing implementations. With intrinsic error correcting capabilities, the GKP qubit breaks the abstraction layer between error correction and the physical implementation of qubits. In [133], we discussed the faul-tolerant preparation of GKP qubits and realistic experimental difficulties. We believe that qubit encodings like the GKP encoding will be useful for reliable quantum computing.

We can further explore the idea of breaking the ISA abstraction. Near-term quantum devices have errors from elementary operations like 1- and 2-qubit gates, but also emergent error modes like cross-talk. Emergent error modes are hard to characterize and to mitigate. Recently, it has been shown that randomized compiling could transform complicated noise channels including cross-talk, SPAM errors and readout errors into simple stochastic Pauli errors [136], which could potentially enable subsequent noise-adaptive compilation optimizations. We believe if compilation schemes that combine noise tailoring and noise adaptation could be designed, they will outperform existing compilation methods.

Near-term quantum algorithms such as Vairiational Quantum Eigensolver (VQE) and Quantum Approximate Optimization Algorithm (QAOA) are tailored for NISQ hardware, breaking the circuit/ISA abstraction. We could take a step further and look at high level algorithms equipped with customized error correction/mitigation schemes. Prominent examples of this idea are the Generalized Superfast Encoding (GSE) [138] and the Majorana Loop Stabilizer Code (MLSC) [139] for quantum chemistry. In GSE and MLSC, the overhead of mapping Fermionic operators onto qubit operators stays constant with the qubit number (as opposed to linear scaling in the usual Jordan-Wigner encoding or logarithmic in Bravyi-Kitaev encoding). On the other hand, qubit operators in these mappings are logical operators of a distance 3 stabilizer error correction code so that we can correct all weight 1 qubit errors in the algorithm with stabilizer measurements. These work are the first attempts to algorithm-level error correction and we are expecting to see more efforts of this kind to improve the robustness of near-term algorithms.

We generally think of dissipation as competing with quantum coherence. However, with careful design of the quantum system, dissipation can be engineered and used for improving the stability of the underlying qubit state. Previous work on autonomous qubit stabilization [135] and error correction [137] suggest that properly engineered dissipation could largely extend qubit coherence time. Exploring the design space of such systems and their associated error correction/mitigation schemes might provide alternative paths to an efficient and scalable quantum computing stack.