Silicon edge-dot architecture for quantum computing with global control and integrated trimming

Each hardware unit cell is constructed around a single silicon plateau which facilitates the formation of quantum dot structures along the plateau boundary while also hosting standard techniques seen in planar device formation in locations away from the boundary as shown in Fig. 1a). These include the formation of implantation regions and carrier reservoirs, tunnel barriers and quantum dots. The quantum dots formed at the plateau boundary take advantage of the electric field concentration in the cross-sectional corner due to the overlapping gate electrode, resulting in strong carrier confinement Voisin et al. (2014); Corna et al. (2018). The length of the gate in the overlapped region acts to confine the quantum dot in the remaining dimension.

A recent scaled architecture proposal Cai et al. (2019) illustrated several advantages of how the integration of a spinless mediator quantum dot Srinivasa et al. (2015); Malinowski et al. (2019) connected to a charge reservoir could facilitate robustness against certain types of leakage errors in the form of physical charge movement, which would otherwise be highly detrimental to a schemes based on repeated execution of stabilizer cycles. A blueprint for a scaled quantum machine utilising the edge-dot approach, producing a 2D array of qubits interconnected via mediator dots, is illustrated in Fig. 1b).

A more detailed picture of the primitive hardware unit cell for this scaled quantum machine is shown in Fig. 1c-i), including the Front End of Line (FEOL) consisting of the physical qubit layer and supporting hardware defined by the silicon plateau, and Back End of Line (BEOL) consisting of routing metal layers for control. Each corner of the plateau is connected to a neighbouring plateau (the next adjacent hardware cell) via a shared nanowire with patterned split-gate elements acting to form a double quantum dot site. These quantum dots can be populated with charge carriers from the reservoir via the mediator quantum dots Cai et al. (2019), and act to house the physical qubits upon which the computations and error correction codes are performed. The charge reservoir consists of an ohmic implantation site illustrated in Fig. 1c) as an exposed central region of the plateau which is directly contacted by a metallic via (black squares in Fig.1d-h). The planar surface of this silicon plateau is further utilised to distribute charge from this central reservoir to each edge through a metallic accumulation gate patterned in polycrystalline silicon (poly-silicon) Layer 1 in Fig. 1d). Tunnel barriers between the accumulated reservoirs and the edge defined quantum dots can be formed either though engineered gaps Rochette et al. (2019); Hutin et al. (2019a) or dedicated barrier gates Yang et al. (2013); Zajac et al. (2018) seen patterned in poly-silicon Layer 2 in Fig. 1d). The plateau edges are overlapped with gate electrodes in poly-silicon Layer 1 which act to confine elongated quantum dots through the concentration of electric fields in the gate-edge overlap region. The plateaus are interconnected at the corners by a narrow silicon channel, commonly referred to as a “nanowire”, where split-gate technology Dupont-Ferrier et al. (2013) is used to form a double quantum dot via features in poly-silicon Layer 1 and tunable tunnel barriers via electrodes in poly-silicon Layer 2. The tunnel barriers are utilised to interface quantum structures formed in the nanowires with those formed at the edges of connected plateaus. For the long plateau edges, a mediator quantum dot is formed Malinowski et al. (2019), which serves to transfer qubit information between the quantum dots at each endpoint Srinivasa et al. (2015); Cai et al. (2019). The mediator dots have the additional advantage of introducing a means through which quantum information processing hardware elements can be physically separated to allow for efficient signal routing and integration of control or sensing peripherals required at the intra-hardware-cell level. In the example illustrated, the mediator dot is required to be $\sim 5\times$ the pitch of the BEOL metal routing, allowing for inter-cell connective routing of the FEOL elements as well as routing between metal layers. Space in the FEOL for integrated peripheral hardware can be seen as the (empty) regions between plateaus (grey), amounting to an area approximately equivalent to the plateaus. A diagram illustrating interconnected plateaus is provided in Supplementary Fig. S1.

For the execution of the surface code cycle, as detailed in § III, two varieties of qubit are utilised simultaneously; single electron spin qubits for data qubits and singlet-triplet qubits for ancillas ($X$ and $Z$ syndromes). For the control of single electron spins, electron spin resonance (ESR) methods have recently shown control fidelities of up to $99.96\%$ utilising optimised pulse schemes Yang et al. (2019) operating over $8$ µs timescales. As shown in later sections, pulse optimisation schemes such as these transfer well to globally applied spin manipulation.

For readout, the effect of Pauli spin blockade on interdot tunnelling Ono et al. (2002); Petta et al. (2005) enables in-situ double-dot readout for the syndrome qubit state, with high fidelity single-shot Pauli spin blockade detected in several implementations of silicon MOS quantum devices Harvey-Collard et al. (2018); Urdampilleta et al. (2019); Zhao et al. (2019). This readout method, combined with gate-based reflectometry measurement techniques Urdampilleta et al. (2019); West et al. (2019); Ibberson et al. (2021) results in a scalable approach to rapidly reading qubit states without the need for integrating additional charge-sensing hardware infrastructure within the FEOL. Some examples in silicon devices have shown readout fidelity of $99.7\%$ in 300 ns Ibberson et al. (2021), with others showing extrapolations to $99.9\%$ fidelity achievable in comparable timescales to the single spin qubit gates  Zheng et al. (2019).

For initialisation, the triplet lifetimes within the spin blockade region is seen to vary based on species, from 200 µs for $\left|{T_{0}}\right\rangle$ and up to 5 ms for polarised triplets West et al. (2019); Seedhouse et al. (2021), however for initialisation of the singlet state, this triplet lifetime can potentially be reduced through the use of relaxation hot-spots Srinivasa et al. (2013); Huang et al. (2019), particularly the spin-orbit driven $S/T^{\pm}_{(1,1)}$ anti-crossings found either side of the primary singlet anti-crossing, or through selective tunneling with nearby reservoirs Maune et al. (2012); Jock et al. (2022).

For two-qubit gates, the nearest-neighbour exchange interaction has lead to several realisations Veldhorst et al. (2015); Watson et al. (2018); He et al. (2019); Zajac et al. (2018); Huang et al. (2019); Sigillito et al. (2019), resulting in scaling proposals based on densely-packed two-dimensional arrays of quantum dots Veldhorst et al. (2017); Li et al. (2018), or protocols involving the transport of qubits along long chains of dots Boter et al. (2019). Other solutions such as photon-mediated two qubit interactions are accessible through hybrid material platforms Borjans et al. (2020); Clerk et al. (2020).

Alternative methods which maintain compatibility with the materials and processes used in the silicon device industry is to mediate a next-nearest-neighbour exchange through empty Baart et al. (2017), or multi-electron dots Malinowski et al. (2019). The mediating structures focused upon here take the form of elongated quantum dots which have nearest-neighbour exchange coupling between itself and a quantum dot at each endpoint (see Fig. 1b,c). This elongated quantum dot does not contain any quantum information and only acts to mediate a next-nearest-neighbour interaction between the two sites at each endpoint through the Ruderman-Kittel-Kasuya-Yosida exchange interactions Srinivasa et al. (2015). For a multielectron dot occupied by the first two electrons (or equivalent S=0 ground-state), the exchange energy $J_{\rm DA}$ between a data (D) dot and ancilla (A) dot, through the mediator (M), is approximated by Srinivasa et al. (2015); Cai et al. (2019)

$$J_{\rm DA}\simeq\frac{t_{\rm DM}^{2}t_{\rm AM}^{2}}{\varepsilon_{\rm DM}\varepsilon_{\rm AM}\delta_{\rm M}},$$

(1)

where $t_{\rm DM}$ ($t_{\rm AM}$) is the tunnel coupling between the data-mediator (ancilla-mediator) dots, $\delta_{\rm M}$ is the excited state energy on the mediator with $\varepsilon_{\rm DM}$ ($\varepsilon_{\rm AM}$) the energy detuning of the data (ancilla) dot from the mediator excited state. A final element required for this scheme is coherent shuttling of a single electron spin qubit between double-dot locations. Shuttling has been shown to have negligible effect on spin projection, with a recent study showing spin polarization is maintained when shuttling between two sites with a fidelity of $>99.9\%$, with $>99\%$ for phase coherence Yoneda et al. (2021). Further, accurate charge shuttling across arrays of up to 9 dots Mills et al. (2019), and relative shuttling uncertainties below 50 parts per million Rossi et al. (2014) have also been demonstrated.

The algorithic unit cell representing the suface code is illustrated in Figure 2a), executing an interleaved XXXX and ZZZZ stabilizer. Utilizing strategic timing for state preparation and measurement of syndromes, the code cycle can be made compatible with the “tick-tock” method of executing algorithms using globally applied single qubit Hadamard gates and selective CZ gates Jones et al. (2018). The effective CNOT operations are highlighted by coloured grouping of Hadamard and CZ gates in Fig. 2a). The use of globally applied single qubit operations results in all unit cells within the quantum machine being controlled by the same input ESR signal. The approach requires embedding the quantum machine within a large peripheral 3D cavity, and the feasibility considerations for this solution is discussed in § IV. The schematic of a single edge-dot hardware cell capable of executing this stabilizer code is illustrated Fig. 2b). To execute the error correction process across the surface of the quantum machine, the unit cell must be interconnected to adjacent cells. This is achieved by positioning the ancillar and data quantum dots on the unit cell boundary, while the mediator dots (which result in the CZ operations between qubit locations), are enclosed within a cell boundary. The inter-cell operations are shown as the grey CZ connections within the surface code protocol in Fig. 2a), executed through the mediators external to the hardware cell boundary in Fig. 2b) where the equivalent dot positions in adjacent cells are indicated by a prime notation (e.g. $X_{1}^{\prime},Z_{2}^{\prime}$).

Much like the primitive cell of a crystal lattice structure, where elements are shared when located at a vertex, edge or face, the unit cell here contains on average 4 dots and (for this implementation) 3 spin 1/2 particles attributed to qubits, plus an additional 4 mediator dots. The two data qubits D1 and D2 bounding the cells consist of a single spin 1/2 particle, each contained within one of two possible quantum dots $A$ or $B$. During the execution of the code cycle, the data spin qubit is shuttled between the dots $A$ and $B$ in order to access and complete all necessary operations between ancillas. In Fig. 2, dot locations D1_A,B and D2_A,B are illustrated, with the physical spin qubits indicated in Fig. 2a) as the solid traces while the empty occupancy of dots are denoted by the dashed traces.

A detailed breakdown of the 12 individual time steps within the surface code cycle seen in Fig. 2a) is presented in Supplementary Note S1. The use of singlet-triplet based syndrome qubits is compatible with the global ESR schemes as the singlet and triplets remain within their spin manifolds under global rotations. This gives rise to additional simplifications to the above protocol, however these have been omitted from the figures for clarity. For example, the initialisation and measurement process for the two ancillas could be spread over all time steps outside the two-qubit CZ operations (i.e inclusive of 9-2 for $X$ and 12-5 for $Z$), which could facilitate additional time in the measurement and initialisation phases without extending the total time required for the code-cycle.

It is asserted that universally applied, or “global”, signals acting as a control input for all qubits across all cells is a desirable property for this approach to scaled quantum systems. Several proposals have also highlighted the potential use of globally applied AC fields for scaled systems of spin qubits, controlling either the entire ensemble of qubits Vandersypen et al. (2017), or sub-ensembles Veldhorst et al. (2017); Li et al. (2018). One approach to achieving this is to embed the silicon devices within a microwave cavity Vahapoglu et al. (2021). Here, the feasibility of achieving sufficiently uniform global control on the ensemble of single qubit spins within the silicon quantum dot array is discussed.

For electron spins in silicon, the spin-orbit interaction is weak when compared to other semiconductors, but still remains appreciable. The surface-roughness of the Si/SiOx interface is predicted to result in an uncontrollable distribution in the Landé $g$-factor of up to $\delta g=\mathcal{O}(10^{-2})$ Ferdous et al. (2018). It has been shown that this value is tunable based on changes in the electrostatic field environment Veldhorst et al. (2014); Hwang et al. (2017); Jock et al. (2018), however this degree of the Stark shift seen experimentally remains $\Delta g\simeq\mathcal{O}(10^{-4})-\mathcal{O}(10^{-3})$ Veldhorst et al. (2015); Hwang et al. (2017). Thus, for a quantum device operating at appreciable applied magnetic field (B${}_{0}\sim 1$T), the Stark shift of the electron $g$-factor can act as a potential source of local tunability, but cannot compensate for the entire $\delta g$ distribution. Therefore, the quantum machine must operate within the limits of broadband microwave pulsing techniques, requiring fields substantially lower than 1T Vandersypen et al. (2017); Li et al. (2018) or otherwise operate with composite pulsing schemes requiring a train of pulses Vandersypen and Chuang (2005). For this proposal, high B₀ fields are necessary for the implementation of the charge leakage protection schemes Cai et al. (2019), however pulse trains that are substantially longer than the single qubit $\pi$-rotation time are an undesirable solution as they can absorb significant fractions of the $T_{2}$ coherence time budget for active qubits. As a compromise, amplitude modulation (AM) techniques can be integrated into the control.

For a quantum gate applied via a resonant microwave AC driving field, it is convenient to define the control signals $I_{0}(t)$ and $Q_{0}(t)$ as the in-phase and quadrature components of an envelope function with carrier frequency $\omega_{0}$ Yang et al. (2019). This carrier is typically set by the Larmor frequency of the individual electron $g$-factor $g_{e}$, here it is set by the mean of the $\delta g$ distribution. In this rotating frame, the qubit control Hamiltonian appears as

$$H_{Q}=I_{0}(t)\sigma_{x}+Q_{0}(t)\sigma_{y}+\delta\omega\sigma_{z},$$

(2)

where $\sigma_{i},i\in\{x,y,z\}$ are the Pauli matrices, and $\delta\omega$ represents the frequency detuning of any single qubit from the mean of the $\delta g$ distribution. Amplitude modulation can be employed as a method to expand the number of resonant peaks in the frequency domain from a single peak at $\omega_{0}$, to multiple sets of side-bands that are frequency-shifted copies of the pulse envelope set by $I_{0}(t)$ and $Q_{0}(t)$. An amplitude modulation scheme which can be utilised to increase the number of resonant peaks output by the cavity from a single peak, to $N$ peaks separated by frequency $\omega_{AM}$ and centred at $\omega_{0}$ is detailed further in Supplementary Note S2. Thus, the Stark shift can operate such that $\delta\omega=0$ for the qubit Hamiltonian in Eq. (2) by tuning the resonant frequency of each electron to the nearest side-band within the set $\omega_{0}\pm n\cdot\omega_{AM}$ for $n\in[0,(N-1)/2]$ (odd $N$) or $\omega_{0}\pm(n+1/2)\cdot\omega_{AM}$ $n\in[0,N/2]$ (even $N$). It is expected that $N\simeq 10-100$ is required to span the frequency bandwidth created by the range of $g$-factor distribution $\delta g=\mathcal{O}(10^{-2})$, given a stark shift range of $\Delta g\simeq\mathcal{O}(10^{-4})-\mathcal{O}(10^{-3})$.

Recent studies have shown how Gradient Ascent Pulse Engineering (GRAPE) techniques Khaneja et al. (2005); De Fouquieres et al. (2011) have been utilised to design broadband pusles that can account for local environmental noise, pushing single qubit control fidelity to the limit of incoherence Yang et al. (2019). For systems in which individual qubit tunability is necessary for the uniformity of global control signals across a large array of qubits, these GRAPE methods can also be viewed as a scheme for mitigating errors in qubit tuning. Figure 3a) shows a GRAPE solution for the $I_{0}(t)$ and $Q_{0}(t)$ envelopes required to produce a Hadamard gate, delivering a high fidelity operation over a larger bandwidth for robustness against tuning errors or small drifts in $\delta g$. The offset error in the tuning via the Stark shift $\Delta g$ which the gate can tolerate for given target fidelity can be seen in Fig. 3b). The solution results in a more complex trajectory over the Bloch sphere as seen in Supplementary Figure S2, requiring 6$\times$ the time of a $\pi$ rotation produced by a square pulse with the same amplitude limits (set as a 1 µs square pulse $\pi$ rotation at $B_{0}=1$T). The resulting GRAPE pulse has better performance against low frequency noise coupled via the $\delta\omega$ term in Eq. (2) as illustrated by the first order filter transfer function in detuning $F^{(1)}_{z}$ Green et al. (2013) as seen in Fig. 3f). Similar to the methods in Ref. Yang et al. (2019), the operation is trained against realistic qubit environmental noise Chan et al. (2018). While GRAPE methods can result in frequency-broadened qubit drive-lines offering a robustness to tuning errors, combining this with amplitude modulation results in the presence of multiple broadened side-bands that can also interfere with each-other. The infidelity of N=10 simultaneously driven peaks as a function of modulation frequency $\omega_{AM}$ is seen in Figure 3c), showing disruptive levels interference between side-bands under small $\omega_{AM}$ peak separations, however a much smaller separation in $\omega_{AM}$ is seen to be required by a solution utilising GRAPE when compared to the square pulse solution. Figure S3 illustrates the full infidelity-envelope for the amplitude modulation method described in Eq. (S1), where N=10 peaks are simultaneously produced. A limit of $\omega_{AM}>4$MHz is observed to gain a region of Hadamard infidelity $1-F_{H}<1\times 10^{-3}$ corresponding to a $g$-factor tunability range of $\Delta g\simeq 4.5\times 10^{-4}$ to move between two neighbouring peaks, or equivalently $\Delta V=22.5$mV utilising $\partial g/\partial V=0.002/V$ motivated from Ref. Veldhorst et al. (2015); Hwang et al. (2017). The requirement on the Stark shift of $\Delta g\simeq 4.5\times 10^{-4}$ falls within the expected range of $\mathcal{O}(10^{-4})-\mathcal{O}(10^{-3})$, although this threshold could be improved through more advanced optimisation acting to reduce the cross-talk.

Pulse engineering methods can also be utilised for two-qubit gates Ball et al. (2021), where the globally applied ESR field can assist in decoupling action from local qubit noise. The mediated exchange energy in Eq. (1) can be incorporated as a voltage controlled signal $E_{J}(t)\propto J_{DA}$ in the following two qubit Hamiltonian:

	$\displaystyle H_{Q2}=$	$\displaystyle I_{0}(t)(\sigma_{x}\otimes\mathcal{I}+\mathcal{I}\otimes\sigma_{x})$
		$\displaystyle+Q_{0}(t)(\sigma_{y}\otimes\mathcal{I}+\mathcal{I}\otimes\sigma_{y})$
		$\displaystyle+\delta\omega_{1}(\sigma_{z}\otimes\mathcal{I})+\delta\omega_{2}(\mathcal{I}\otimes\sigma_{z})$
		$\displaystyle+E_{J}(t)\left(\begin{matrix}0&0&0&0\\ 0&-1&0&0\\ 0&0&-1&0\\ 0&0&0&0\end{matrix}\right),$		(3)

where $\mathcal{I}$ is the identity matrix in the single qubit subspace and $\otimes$ represents the Kronecker product. The component of the Hamiltonian in Eq. (3) responsible for interaction between spins is valid for $|E_{J}(t)|_{\rm max}\ll E_{Z}$, Meunier et al. (2011) and has been demonstrated to produce effective CZ operations Veldhorst et al. (2015); Watson et al. (2018). The pulse shapes in Fig. 3d have been designed such that when $E_{J}(t)$ is applied with global $I_{0}(t)$ and $Q_{0}(t)$ signals, the resulting operation is a decoupled CZ operation. In contrast, when $E_{J}(t)$ is not applied, i.e. for $E_{J}(t)=0$, the global $I_{0}(t)$ and $Q_{0}(t)$ signals result instead in a decoupling identity gate applied to both independent spins. The infidelity of the decoupled CZ and Identity gates as a function of qubit detunings $\delta\omega_{1}$ or $\delta\omega_{2}$ (referred to a single electron $\delta g$ offset) is shown in Fig. 3e). The GRAPE solution is contrasted against a simple square pulse in $E_{J}$, showing improved robustness against tuning errors up to fidelity targets of $~{}99.99\%$, which is above the threshold for a surface code implementation Fowler et al. (2012). The resulting 1Q and 2Q GRAPE pulses also have improved performance against low frequency noise coupled via the $\delta\omega$ terms in Eq. (2) and Eq. (3) compared to Square-pulse implementations, as illustrated by the first order filter transfer function in detuning $F^{(1)}_{z}$ Green et al. (2013); Ball et al. (2021) as seen in Fig. 3f).

The introduction of the Stark shift as a means of tuning individual spins to a nearby resonance peak gains the ability to perform global qubit control. However this approach results in the transformation of the problem from simultaneously controlling an ensemble of qubit frequencies into one of requiring to provide as many tuned voltage references as there are qubits in the quantum machine. In effect, transferring the scaling problem from a “frequency crowding” problem into a “signal bottleneck” problem Franke et al. (2019).

In order to achieve complete uniformity across all unit cells, the device variation must be addressable at the intra-cell level, resulting in a need for the integration of circuitry fit to address this variation. Here, the additional integrated circuitry is referred to as a “trimmer” circuit and is proposed to consist of a flash-memory-like device. Such a solution can take advantage of desirable characteristics including long-term stability and non-volatility of these integrated circuit elements, to retain voltage set-points over the lifetime of the quantum machine Hasler et al. (2021). Figure 4 illustrates a circuit schematic diagram showing two potential methods for the working principles of the trimming circuit; Fig. 4a) which operates as a source follower (buffer circuit) configuration through reduction of the single setpoint voltage $V_{DD}$ through resistive division and Fig. 4b) which operates through supplying the stored potential as a direct reference for the quantum device. The resistive element $R_{D}$ within the equivalent circuit of a single quantum dot, is produced by the cumulative gate leakage to ground present in CMOS processes Schaal et al. (2018). The circuit elements $M_{\rm T(a,b)}$ shown in Figure 4 are central to performing the trimming, possessing salient characteristics similar to that of a floating-gate MOSFET including a tunable threshold voltage and non-volatility.

By trimming the threshold voltage of the device, the channel resistance in deep sub-threshold operation of the device $M_{\rm T(a)}$ in Fig. 4a) can become comparable to $R_{D}$, resulting in an active voltage division which reduces the value of $V_{DD}$ down to some desired value (which is presumed in this instance to target a qubit resonance line though the Stark shift discussed in § IV). A more detailed feasibility study of this resistive trimmer configuration is presented in Supplementary Note S3. The threshold voltage is tuned through charge storage within the device, converted to a voltage through the capacitance relationship. For $M_{\rm T(b)}$ in Fig. 4b), the stored charge within the device can be more directly converted into a voltage reference in a similar fashion to a previous proposal utilising dynamic random access memory (DRAM) Veldhorst et al. (2017). Here, the voltage reference is delivered directly to the quantum device through a direct connection between the gate electrode defining the quantum dot and the charge storage element within the memory component $M_{\rm T(b)}$. For the solution shown in Figure 4, three additional MOS devices must be integrated for each trimmed object within the unit cell. A cross-bar addressing scheme is utilised for individual trimming devices $M_{\rm T(a,b)}$ across the unit cell, which becomes active during a pre-computation tuning phase for the quantum machine. The threshold voltage is selectively tuned through signal input $V_{P}$ which is connected, through activated $M_{P}$, to the $M_{T}$ trimming devices. Word-line and bit-line voltage $V_{WT}$ and $V_{BT}$ combine through tuning-enable transistors $M_{ET}$, activating a selected $M_{P}$. Based on the hardware unit cell architecture discussed in § I, the elongated mediator dots which interconnect data and ancilla qubits allow for a certain amount of physical space Cai et al. (2019) in-between the silicon plateaus where these devices can be laid out in the FEOL layer, avoiding vertical circuit integration in the form of stacking control transistor layers above the the quantum FEOL Veldhorst et al. (2017). The characteristic of non-volatility assumes operation within a consistent thermal environment and is deliverable by standard MOS memory hardware Hasler et al. (2021). This is essential for the device $M_{\rm T(a,b)}$ as, after tuning each device to the desired set-point, the selector crossbar-architecture as shown in Fig. 4 becomes idle, allowing the circuitry to be powered down more completely, reducing latent power consumption or heat load. Stability characteristics of the device must be such that the set memory state does not drift appreciably over time, as this would contribute to errors in $\Delta g$. In this instance the stability requirements are defined by the high-fidelity region of the broadband pulses discussed in § IV.

Here, a solution is proposed to manage resources at the quantum-classical interface within a scaled processor through integration of MOS structures at the FEOL quantum hardware level. The additional hardware is required to combat device-to-device variation which is a principle challenge when scaling quantum machines Laucht et al. (2021). The different aspect ratio between the qubit layer and the data processing layers can also complicate this quantum-classical interface Veldhorst et al. (2017), which can be avoided through the use of elongated mediator dots Cai et al. (2019) or shutting qubits through 1D dot chains Boter et al. (2019), as well as de-embedding single qubit control to be executed globally via a 3D microwave cavity Vahapoglu et al. (2021). This scaled quantum machine can be achieved through the hybridisation of SOI nanowire technologies Hutin et al. (2019a) with planar quantum dot structures Yang et al. (2013), producing an “edge dot” platform where the quantum dots are defined at the geometric boundary of a raised silicon plateau.

The hardware cell presented here is also extremely flexible, with the capacity to be re-configured to operate the surface code for different control schemes. For example, forgoing globally applied ESR of electron spins in the pursuit of an all-electrical control scheme can still utilise this same hardware architecture, with the addition of integrated micromagnet arrays Singh et al. (2020) into the FEOL. This approach can potentially utilise the space outside the plateau in each alternating cell to incorporate diagonally aligned micromagnets between the data qubit locations. This produces an engineered magnetic field gradient across each data-qubit double-dot, which can facilitate single qubit rotations Pioro-Ladriere et al. (2008). In combination with the capability of tuning the stark shift via the trimming circuit, the amplitude modulation scheme presented here is also directly transferable to a globally applied EDSR control signal for this implementation.

The type of qubits used in this hardware is also flexibly defined, based on the configuration and number of charges within each double-dot site. It is shown here that this architecture can facilitate a co-existing combination of single-electron spin qubits and two-electron Singlet-T₀ Triplet qubits. A similar micromagnet configuration as the one discussed above could also be utilised for an all-electrical control implementation with both data and syndrome qubits defined in the singlet-triplet basis Wu et al. (2014). However, it is noted that approaches involving micromagnets can constitute a deviation from the materials used in the CMOS industry. Without the integrated micromagnet array, all-electrical control can still be achieved in silicon via several implementations. Single-hole spins with EDSR control Maurand et al. (2016) leverage higher spin-orbit couplings compared to electrons and singlet-triplet qubits can rely on the naturally present spin-orbit coupling for single qubit rotations Jock et al. (2018, 2022). Other all-electrical qubit species involve a (2,1) electron occupancy for the hybrid qubit implementation Shi et al. (2012) and (1,0) occupancy for qubits defined in the charge basis Hayashi et al. (2003). Note that for each of these qubit implementations listed above, tailored control schemes implementing the achievable gate-sets for these qubit varieties must be devised and are considered out of the current scope of this study.

A unit cell approach to constructing scalable quantum information processors benefits from a drasitic reduction in input overheads due to high levels of parallelisation between each cell. These hardware-based unit cells can also strongly compliment the tile-like nature of many error correction codes applied to 2D lattices of qubits. In order to successfully carry out this goal, it is necessary to tailor the design and execution towards the use of global signal control strategies such as noise-robust pulses and parallelisation schemes. From the hardware perspective, this also requires the integration of robustness against inter-cell device variations. For any scaled qubit implementation, the variation in qubit control parameters must be overcome. In the case of single electron spin qubits, utilising a 3D cavity as a control peripheral Vahapoglu et al. (2021) in which the silicon chip is embedded allows for many qubit to be addressed across a large spatial range. However, contemporary results in planar MOS devices show the expected distribution in the electron $g$-factor Ferdous et al. (2018) far exceeds the range available through Stark-shift tunability Veldhorst et al. (2015); Hwang et al. (2017); Huang et al. (2019). Thus, the concept of tuning via stark shifts must be augmented when operating at appreciable magnetic fields for global operations to be applied to the spin ensemble. Here, the solution presented involves the use of amplitude modulation for the production of discrete side-bands, with the Stark-shift providing individual $g$-factor tuning towards the nearest band. This approach is subject to a trade-off between the separation between the side-bands given a certain tunable range in $g$-factor, and the cross-talk between side-bands observed at small separations. As shown here, the same engineered pulses which increase robustness against small tuning deviations in the $g$-factor can also result in reduced cross-talk between side-bands compared to equivalent square-pulse implementations. With the added design element of intentionally reducing cross-talk between side-bands within the optimisation process, this trade-off between cross-talk and Stark-shift could be further improved. The signals executing the CZ operation can also be made compatible with global control operations through the electrical tuning of the exchange energy between features in the unit cell. Tuning the Stark shift will result in alterations to the $\varepsilon_{\{D,A\}M}$ terms in Eq. (1), however by tuning of the potential on the barrier gates situated between the Dots and the Mediators in Fig. 2b) can compensate via directly tuning the $t^{2}_{\{D,A\}M}/\varepsilon_{\{D,A\}M}$ ratio, ensuring uniformity in $J_{DA}$ across all sites. The magnitude of $J_{DA}$ can then be modulated through signal $V_{M}$ applied to the Mediator accumulation gate, which has a linear relationship to both $\varepsilon_{DM}$ and $\varepsilon_{AM}$, resulting in $J_{DA}\propto V_{M}^{-2}$

For the global control solutions presented here, the surface code cycle is executed within $\sim 46$ µs ($5\times\tau_{H}+4\times\tau_{CZ}$), assuming near-negligible electron shuttling times Yoneda et al. (2021). This is well below the state-of-the-art single-spin coherence time of $T_{2}^{RB}=9.4$ ms Yang et al. (2019) as derived from a Randomized Benchmarking experiment utilising GRAPE pulses. The collective ancilla qubit measurement and initialisation time for this protocol is 12-28 µs depending on the implementation. Current measurements in silicon nanowires have lead to the determination of a PSB signal with $>$99% fidelity within 5.6 µs Oakes et al. (2022), leaving approximately a 6-22 µs budget for $\left|{S}\right\rangle$-state initialisation via mediator/reservoirs in the first instance. This time budget can also be extended over multiple code-cycles if necessary, through adopting plaquette sequencing protocols discussed in Ref. Cai et al. (2019).

Focusing on the mature CMOS industry for the development of quantum processors has the core benefit of being able to draw upon many different advancements and techniques for information processing and storage Gonzalez-Zalba et al. (2021). A similar approach for addressing device variation includes embedding a quantum machine into a DRAM-style circuit Veldhorst et al. (2017), where the 6T3C/dot cell stores a pre-tuned voltage supplied from a variable source on a capacitor near each quantum dot, and refreshed over a cyclic period. For this approach, the hold-capacitor must be large enough for a sufficiently stable voltage (and thus resonant frequency via the Stark shift in the $g$-factor) for high fidelity qubit operations. Conversely, this capacitive element must also be small enough not to dominate the integrated dispersive readout signals Schaal et al. (2019). In contrast, the method presented here proposes the specific integration of non-volatile memory elements for the storage of these pre-tuned voltage settings. These voltage references are continually applied by the non-volatile elements and are therefore not subject to the same limitations set by capacitive decay constants or cycle-to-cycle variations, but will still be limited by Johnson noise generated by the voltage reference elements in a similar way. Both approaches, however, require a potentially high set-up cost represented by a pre-computation trimming phase which identifies the correct operating conditions for each qubit element, however an advantage for the implementation presented here is that this tuning circuitry has the option to become dormant during computation phases due to the non-volatility of the integrated memory elements, potentially reducing the latent power consumption of the device.

With the addition of trimming internal to the hardware unit cell, the number of inputs required to set the state of the quantum machine can be drastically reduced through the interconnection of cells. This results in a hardware in which the number of inputs scales with the complexity of the unit cell, rather than the number of unit cells required to produce the quantum machine Franke et al. (2019), ensuring the extensibility of the qubit platform. The physical layout of the CMOS elements in the FEOL, and the routing between the elements at the quantum-classical interface, is considered to be out of scope for this initial work, however for the solution presented in § V, 48 elements are required per unit cell to connect 16 structures which require trimming (the reservoir accumulation gate, and barriers between the mediators and reservoir are discounted here, as these do not require precise tuning to function). As the area between silicon plateaus is $\sim(8\times p)^{2}$ for the direct routing solution presented in Fig. 2, where $p$ is the BEOL routing pitch, this affords an area budget of $\sim 1.3p^{2}$ per control element before the size of these elements impacts the length of the mediator dots which are $\sim 5\times p$ in this example. A potential alternative method for spin transfer would be to replace the mediator with a spin-shuttling chain of quantum dots, which has been studied elsewhere Boter et al. (2019), and has different trade-offs regarding increased numbers of electrodes and control signals.

While the extension of this architecture towards lattice surgery methods is also considered out of the scope for a study of the individual hardware cell, it is noted that a deviation from globally applied electrical control signals towards grouping regions of the surface into distinct areas, perhaps governed by separate DACs, can facilitate lattice splitting and merging required for lattice surgery Horsman et al. (2012). For example, inactivity of CZ mediator signals along a selected row/column results in dormant regions in the surface structure, producing a split between two distinct regions. Further, it is also feasible to have intermittently placed, dedicated control circuitry offsetting entire regions of quantum unit cells in the FEOL, as the surface code has been shown to be robust against both time-resolved, and/or spatial interruptions defects Strikis et al. (2021). The exact geometric topology and layout of the quantum VS classical regions in the expanded FEOL is considered to be beyond the scope of the unit cell as studied here.

Defining a hardware unit cell which is complimentary to a specific stabiliser code cycle can lead to a highly parallelised approach to the execution of large scale quantum information processing. Here, a case study is presented which utilises a hybrid between two prevalent silicon MOS technologies, combining the advantages of current state-of-the-art solid-state quantum hardware approaches with memory storage techniques. The choice of design to include integrated mediator quantum dots makes the stored quantum information additionally robust against leakage error types which cannot be protected against through standard quantum error detection protocols. The adapted code-cycle presented here allows for the implementation of globally applied single-qubit rotations across the entire ensemble of qubit resonant frequencies, as well as selectively applied two-qubit CZ operations from a global signal source. The inclusion of non-volatile memory elements within the hardware unit cell also reduces the signal overheads to expand with the unit cell size rather than with the number of cells. The result is a complete unit cell approach to constructing a robust quantum information processing machine of arbitrary scale in silicon.

The author would like to thank J. J. L. Morton, M. F. Gonzalez-Zalba, S. C. Benjamin and Z. Cai for valuable discussions and comments on the manuscript

The Author is supported by Quantum Motion, a start-up developing silicon-based quantum computing.