The design and performance of the ZEUS Micro Vertex Detector

The HELIX 128-v3 chip has been selected for the frontend readout. The HELIX was originally developed by the ASIC Labor Heidelberg for the HERA-B experiment. It was designed in $0.8\,\,\upmu\textrm{m}$ CMOS technology and was manufactured by AMS [14]. In the following only the general features of the HELIX chip are described. More details can be found in [6, 15].

One HELIX chip contains 128 channels, each having its own charge-sensitive preamplifier, a shaper and a 141-cell analog pipeline. The bias settings and various other parameters which determine the shaping time, signal and gain can be adjusted using programmable DACs. The chip runs at $10.41\,\textrm{MHz}$ clock speed synchronized to the HERA bunch crossing cycle. Roughly speaking, it works in the following manner: Once receiving a trigger, the corresponding 128 analog data signals in pipeline cells are sent out over a single analog line synchronized with the clock. At the end of the transfer, an 8-bit trailer encoding the cell location is generated. Several chips can be daisy-chained. In that mode, signals from several chips are multiplexed and read out over one analog line. In case of ZEUS, 8 chips are chained together.

Four chips are hosted on a ceramic hybrid board which provides bias and supply voltages and routes control and output signals. The sensors are connected to the hybrids through a flexible Upilex cable and a glass pitch adaptor. A photograph of a barrel half module attached to a pair of sensors is shown in Figure 2.

Figure 3 shows a sketch of the readout chain of the detector downstream of the detector modules. Supplies and signals as well as sensor lines for temperature and humidity are routed along the rear part of the ZEUS beampipe over a distance of ca. $6\,{\rm m}$ using customized “COMBO” cables made by Axon [16]. In the barrel the connection between the ceramic hybrids and the COMBO cables is done using a $500\,\upmu\textrm{m}$ pitch flex PCB and miniature ZIF connectors. This solution was chosen due to the severe space constraints. In the forward section of the detector these constraints are less severe and hence standard PCBs were chosen. Just outside the ZEUS detector on the rear side the COMBO cables are connected to four patch boxes where bias and supply voltages as well as data and control cables are split up. The COMBO cables provide double shielding and in addition groups of COMBO cables are routed inside conductive zipper tubes for additional protection against electromagnetic interference. Also, the cables running from the patchboxes to the readout racks some $20\,{\rm m}$ away are doubly shielded. This careful shielding allowed to keep the entire analog signal chain from the sensors to the backend readout system outside the detector without active elements. This approach was deemed necessary since the frontend of the detector is not easily accessible and it was planned to operate it for a period of five years without intervention. In retrospect this approach has proven very successful.

The total number of analog signal lines in the detector amounts to 206. Each HELIX chip also provides an analog dummy output which follows almost identical circuitry but is not connected to the sensors and lacks the first preamplification stage. Both outputs of the HELIX daisy-chain are subtracted and amplified by an analog link board which feeds it to the ADC module. This analog subtraction takes care of the dominant contribution of the common noise. After the subtraction the signal range is $0\,-\,2\,{\rm V}$, which corresponds to $0\,-\,10\,{\rm MIP}$.¹¹11 MIP corresponds to about 24,000 electrons at the amplifier input.

The ADC module design is described in detail in [17]. Only a brief description is given here. A schematic view of the ADC module is shown in Figure 4. One ADC module processes 8 analog input channels. Each ADC unit (ADCU) handles one analog input line. It consists of a 10-bit analog-to-digital converter (AD9200) and a data processor implemented in a programmable gate array (the XC4028EX of XILINX). The processed data are stored in FIFOs. A data formatter, implemented in another XC4028EX, reads out the FIFOs of all ADCUs and writes formatted data into data buffers, which are accessible from the VME bus.

The data processor in the ADCU is similar to that described in [18]. The block diagram of the data processor is shown in Figure 5. First, 10-bit ADC data are processed for pedestal and common mode subtraction. (At this level, after the analog subtraction in the Analog Link, the common noise is typically very small.) Then, strips with charge greater than a seed threshold are kept for cluster finding. A second cluster threshold is set for the total charge of the cluster before further data reduction. The size of the input raw data volume is reduced to about 2% after the threshold cut and to about 0.1% after the cluster cut. An ADCU has 3 FIFOs for the output data: for raw data, for strip data which consist of strip ID and ADC values after the processing, and for cluster data which contain the total charge and the location of the cluster.

The performance of the analog part is monitored with the internal charge injection of the HELIX which generates a repetitive pattern equivalent to +2MIP, +1MIP, -1MIP and -2MIP in each channel. The digital processing part is tested separately with digital test patterns stored in memory implemented in the module.

The clock and control system (C&C) consists of three parts: These are the master and the slave timing controllers, the helix driver modules and the active electronics inside the patch boxes. Figure 6 shows a schematic of the system. In the following the major components of the system are briefly described. Many more details may be found in [19].

The master and slave timing modules handle the fanout of the trigger and clock signals from the ZEUS Global First Level Trigger (GFLT). The main functions of the C&C master are to receive the standard GFLT information and to pass it on to the C&C slaves, decode the trigger information in order to produce and send the relevant signals to the HELIX fanout modules together with a correctly timed $96\,$ns clock and to handle the ERROR and BUSY signals from the ADCs. Additionally, the C&C master is able to operate in a stand-alone mode for test purposes, generating its own $96\,$ns clock. The C&C slaves receive the GFLT signals from the C&C master and distribute them to all the ADCs within their crates and they receive back the BUSY and the ERROR lines from the ADCs. They also distribute the suitably timed $96\,$ns clock synchronously to all the ADCs in their crates, via a specially wired-in set of 16 twisted pairs of identical length, to front panel connectors. The C&C slaves also allow a continuous VME read access to a register with the ADC-produced signals. Additionally, the C&C slaves can operate with the C&C master as a standalone system for test purposes.

16 Helix Driver Modules are located in a separate VME crate. Each Helix Driver module generates the required controls signals for 15 Helix channels from the clock and control commands received from the C&C master via two Helix Fanout modules. Programming information for the Helix modules in the detector is sent along the VME back-plane to the Helix Drivers, then after some processing to the Patchboxes and on to the detector. The five C&C signals are CLOCK, TRIGGER (this doubles as the Serial Data line during downloading), TEST PULSE, LOAD and $\overline{\texttt{RESET}}$.

Each Helix Driver board carries two Programmable Logic Devices (PLDs), one of which contains the VME interface electronics, and the other, the on-board processing logic, status registers, etc. The incoming signals are treated as follows: The clock signal is fanned to 15 clocks, one for each channel, and each with its own programmable delay unit. The purpose of these is to remove timing skews at the detector. The trigger signal is counted, then OR-ed with the serial data line used for downloading. The combined signal is then sent to all 15 channels. The test pulse is expanded to 15 channels, which are compared with a mask register, then the unmasked ones output to selected channels. The $\overline{\texttt{RESET}}$ is OR-ed with an internally generated $\overline{\texttt{RESET}}$ signal used during downloading. The combined signal is sent to all channels.

The C&C boards in the patchboxes both have active components. The five signals per channel arriving from the Helix Drivers are slightly degraded at the end of the 20 meter cables, and in the case of the clock boards, the signals are re-generated by a receiver-transmitter combination (LVDS to $3.3\,{\rm V}$ CMOS/LVDS) before being sent down the micro-cable twisted pairs to the Helix Modules. This precaution is necessary due to the relatively high attenuation factor of the micro-cables.

The mechanical layout of the MVD consists of a barrel and a forward section. A sketch of the cross section along the beam line is shown in Figure 7.We recollect that the ZEUS coordinate system is right-handed with the $Z$-axis along the incoming proton beam direction, the $X$-axis in the horizontal plane pointing to the inside of the HERA ring and the $Y$-axis pointing upwards.

The barrel section, centered at the interaction point, is about $63\,$cm long. The silicon sensors are arranged in three concentric cylindric layers. As shown in Figure 8, approximately 25% of the azimutal angle is covered by only two layers due to limited space. The polar angular coverage for tracks with three hits ranges from 30⁰ to 150⁰. The modules in the forward section are arranged in four vertical planes extending the angular coverage down to 7^∘ from the beam line. Exits for cables and cooling is arranged from the rear. Many details, design drawings and pictures can be found in [20].

Details on the silicon sensors, their characteristics and performance are described in Section 2.

Two sensors are glued together and one sensor is electrically connected to the other as shown in Figure 10, forming a half module. For various reasons we chose to orient the readout strips of the two sensors within one half module perpendicular to each other as shown in Figure 10. A Cirlex [21] strip ($5.8\times 65.44\,\textrm{mm}$, $0.4\,\textrm{mm}$ thick) glued at the edge in between the sensors, forms the mechanical connection between the two. The use of this material ensures a good insulation of the HV side of one sensor from the ground plane of the other one.

While the sensors overlap by $4.8\,{\rm mm}$, the sensitive areas only overlap by $2\,\textrm{mm}$. Cirlex feet, with a cross section of a few square mm and varying in thickness from 0.8 to $2.4\,\textrm{mm}$, are used to connect the sensors to the support structure.

The electrical connection between the two sensors is made via copper traces on a $50\,\upmu\textrm{m}$ thick Upilex foil. The foil is precisely aligned, glued on the sensors and subsequently wire bonded to the strips. The connection of the sensor assembly with the frontend readout is also made via a Upilex foil, glued at one side on a sensor and at the other side on the hybrid as indicated in Figure 10.

A surface of $123.68\times 64.24\,{\rm mm^{2}}$ forms one readout cell of 512 channels and is called a half module. A mirror image of this half module is also shown in Figure 10; both are mounted on top of each other, separated by the spacers mentioned above forming a full module with 1024 readout channels.

Two precision markers, glued to each half module, provide reference points for the alignment on the support structure.

Apart from their shape the silicon sensors covering the forward region are similar to the barrel sensors as described in Section 2. Fourteen wedge-shaped sensors cover a circular plane around the beampipe. Figure 14 shows the geometry of one sensor, together with the Upilex foil guiding the signals to the hybrid. The strips run parallel to one tilted side; each sensor has a total of 480 readout strips with $120\,{\rm\mu m}$ readout pitch. Figure 15 shows the geometric layout of the sensors for one wheel.

The FMVD consists of four planes perpendicular to the beam axis; each plane has two sensor layers. Adjacent sensors are displaced perpendicular to the beam line by $3\,\textrm{mm}$ and overlap in azimuth by $4\,\textrm{mm}$ ($2\,\textrm{mm}$ in sensitive area). The two layers are mounted back to back on a support structure, separated by approximately $8\,\textrm{mm}$ in Z-direction. Figure 16 shows a sketch of the layout of one half of a wheel. The sensors are mounted on an L-shaped carbon fiber half ring, with seven straight sections. Aluminum inserts in the short ’leg’ of the ring guarantee precision holes for the positioning of the sensors. These are put back to back, such that the angle between the strips is $2\times 13^{\circ}$. The long side of the L-shaped support provides housing for the cooling pipes and supports the hybrids. The half wheels are supported at three points inside the main support tube.

Tab. 4 summarizes the main parameters of the wheel geometry and the statistics of the individual parts.

Figure 17 shows four half wheels mounted in the support structure.

The material distribution has been calculated for individual modules and complete ladders and is summarized in Figs. 18 and 19. If all the material which makes up a module is equally distributed over its surface, the total thickness represents $1.4\,{\rm\%}$ of a radiation length; for a ladder this amounts to $3.0\,{\rm\%}$ (including the modules).

Simulation studies on data multiplicity and background had shown that the MVD data alone, providing up to 3 planes of information per track, would not be sufficient for unambiguous tracking and efficient rate reduction. Combining the MVD information with the surrounding tracking detectors would instead allow a far better rate reduction and tracking efficiency. These considerations have lead to the design within the MVD data acquisition system of the Global Track Trigger (GTT) [24], a distributed computing environment processing data from the MVD, the Central Tracking Detector (CTD) and the newly installed forward Straw Tube Tracker (STT).

For the computing infrastructure, the preferred choice has been to use whenever possible, commercial off the shelf equipment easily upgradable and maintainable. Investigations on the performance achievable in terms of data throughput, process latency and performance suggested a solution based on embedded VME computers running a realtime operating system for the data readout and a farm of standard PCs connected via a Fast/Gigabit Ethernet network for trigger and data processing.

For the readout platform Motorola PowerPC single board CPUs and the LynxOS operating system were chosen due to the following requirements:

• •

  Realtime Unix-like operating system;

• •

  Network boot and diskless operation;

• •

  Reliable Fast Ethernet network operation;

• •

  Fast and flexible DMA and Interrupt capable VMEbus bridge.

28 MVD ADC modules are organized in three 9U VME crates for BMVD upper, BMVD lower and FMVD respectively. These crates receive clock and trigger information via the Clock and Control Slave Module located in the same crate. This system is described in more detail in Section 3.5. A short overview is repeated here. Busy and error conditions are set by the ADC modules and the VME processor and sent through the Slave Module to the Master Module. The Master module is directly connected to the GFLT, and transmits clock and trigger information both to the readout and to the MVD front end and can be operated via VME to allow standalone MVD running. Data gathering from the CTD and STT systems, both of which are based on a network of transputers²²2INMOS Transputers, were an advanced technological development in the late 80’s when the ZEUS experiment was designed. Provided with a 32 bit processing unit, on board memory, four 20 MHz serial links for processor interconnection and a high level parallel programming language (OCCAM), transputers were ideal for highly distributed parallel processing and data transfer. hosted in several VMEbus crates, is done using the same VMEbus computers [25].

On GFLT accept, event data from MVD, CTD and STT are sent to one GTT processor where the required trigger calculations are performed. The GTT result is forwarded to another PowerPC VME computer which re-orders the events according to the GFLT number and transfers the result to the GSLT. Since the GSLT is also based on a transputer network a similar solution as for the CTD and the STT was adopted. No special hardware is required to receive the GSLT trigger decision as this is transferred back via TCP/IP. An interface process forwards it to the MVD readout CPUs and the GTT processors. On GSLT accept the full MVD and GTT data are sent to the EVB interface. It merges and formats these data into the final format. Performance and data quality monitoring is also performed on this system. The specific hardware components of the MVD DAQ and the GTT systems are summarized in Table 5.

In order to fully exploit the VMEbus access capabilities of the on-board Tundra universe II VME bridge, a dedicated software package for VMEbus access on Motorola PPC boards running LynxOS was developed [26]. The package consists of a library layered on an enhanced driver with respect to the default version distributed by LynxOS, providing flexible VME memory mapping, DMA transfer and queueing, VME interrupt and process synchronization control in a multi-user environment. User programs perform all VME and related operations using the library without any direct connection to the driver.

Within the library, basic data structures to describe Shared Memory Segments opened both on the internal contiguous memory and on the VMEbus are available for standard and DMA-controlled read-write cycles. An additional interface is provided to support process synchronization by waiting on, or setting system semaphores. It is possible to connect VME interrupt handling to system semaphores, identically treating synchronization to hardware interrupts, DMA cycles or software signals. The ability to uniquely identify segments by ID or name allows many processes to connect to already existing mapped regions (up to eight in the VME space) without overloading the system. These features have allowed a modular design in a complex DAQ environment. A diagram of the main processes running on the VME computers when taking data is shown in Figure 20.

On the ADC systems two software pipelines running at FLT and SLT rates respectively, exist. At FLT rate the readout program running at lower priority, is woken up on VME interrupt as soon as data are ready on the ADC boards. After data has been transferred via DMA to internal memory, the network tasks, synchronized by a semaphore and running at a higher priority, will send the data to the GTT farm. A similar software pipeline is available also on the CTD and STT interfaces for the data read out at GFLT rate.

The GTT, as any of the components participating in the ZEUS second level trigger, has to process events at an average rate $\leq 600\,\textrm{Hz}$ with a mean latency, including all the data transfers, of less than $10\,\textrm{ms}$ and small tails due to busy events or performance fluctuations.

The GTT environment process is a multi-threaded program with one thread per input data source ($3\times$MVD, $2\times$CTD, $1\times$STT), one thread per trigger algorithm and a time limit thread. Typically one environment runs on each of the dual CPU farm PCs. The scheduling of dispatching data to environments is organized using a synchronized ordered list rather than a round-robin scheme. The decision for that mechanism was based on simulation studies.

For development and performance tests a playback capability has been provided: This allows one to feed simulation or previously saved events into the component VME interfaces and into the GTT trigger chain.

All network data transfers are performed using standard TCP/IP protocol. To cope with the different platforms involved (PowerPC for the VME readout and standard PC for the DAQ and GTT computing nodes) the communication and synchronization is done via short XDR encoded messages while detector data is sent with no additional overhead. To monitor the readout latencies and network transfer times precisely, a general purpose 6U VME board [27] providing a latency/clock register, has been developed and installed in all VME crates and connected to a common $16\,{\rm\mu s}$ clock bus. Thus absolute timestamps and latency measurements are available for every event and stored in the data at several points of the data acquisition phase. This allows a detailed monitoring of the system performance. During normal running a mean latency smaller than $10\,\textrm{ms}$ with steep tail for the whole GTT system, compatible with the initial requirements is observed.

As described previously the DAQ computing environment consists of VME board computers running LynxOS and Intel PCs running Linux interconnected via point-to-point Fast or Gigabit Ethernet. The VME systems are diskless and are booted over the network from a single, dedicated, VME system acting as a boot server. All Linux systems are booted from local disks. In order to simplify code usage a single DAQ file system, containing executable directories etc., is mounted via NFS by all participating hosts.

Standard C programming has been used throughout the DAQ and GTT systems. A number of ROOT-based C++ GUIs have been developed to control the DAQ system in stand-alone mode, to view online or archived histograms, and to manually control the detector slow control system, etc.

All non-readout or trigger data messages are transmitted through a hub process and not directly between processes. The hub is a multi-threaded process which accepts connections at a known address and enforces a simple protocol, using XDR.

The MVD run control can run in either standalone mode or as part of the ZEUS run control system. In both cases process control, stopping and starting tasks, is facilitated by daemon processes started at boot time. These advertise themselves to the run control system and identify, by name, processes they are capable of running. Run configuration requests from ZEUS or the standalone run control specify a Runtype definition file naming all the processes to be started or stopped, the parameters they require, their required exit status, etc. The C preprocessor (cpp) is then invoked to expand all of the definitions contained in the file (resolving required processes, their supporting daemon, startup parameters, etc.). The file produced corresponds to a sequential list of process control commands required to perform all the transitions specified. The run control system can then sequence all the steps required for each transition request received. Transition requests fail if a process fails to reach or does not remain in its final state.

A commercial high voltage system [29] is used to provide bias voltage to the silicon detectors. Four 6U EURO crates (ISEG ECH 238L UPS), with eight voltage boards (ISEG EHQ F0025p) of 16 outputs each provide the 412 channels that are required to supply each silicon half module independently. The output voltage range is 0 to $+200\,$V, adjustable in steps of $5\,$mV. The maximum current is $0.5\,$mA. The nominal detector bias voltage and trip settings were $60\,$V and $50\,{\rm\mu A}$, respectively. The measurement resolutions of $10\,$nA and $5\,$mV allow accurate detector I-V curves to be generated for use in monitoring radiation damage. Two CANbus buses are used; one to connect the four crate controllers, and another to connect the voltage boards via the crate backplanes.

An additional non-crate mounted voltage board supplies the MVD radiation monitor diodes. This device is connected separately to CANbus.

The ability to control the properties of single and groups of output channels simultaneously was used extensively during commissioning of the detector. During data taking this flexibility was not required.

The frontend hybrid low voltage system is a custom development derived from the system used by the ZEUS Leading Proton Spectrometer detector [30]. Six 6U EURO crates, each with 8 voltage boards of 10 outputs provide the 206 channels required to supply $\pm 2\,$V to each hybrid board with a maximum current of $1\,$A. CANbus is interfaced to the internal ${\rm I^{2}C}$ bus at the crate controller board.

An additional crate, whose boards are modified to output $\pm 5\,$V and $\pm 2.1\,$V, is used to supply voltage to the Helix clock and control interface electronics. The CANbus of this crate is connected to the bus used by the hybrid low voltage system. More details can be found in [31].

As with the bias system, single channel control was useful during commissioning the detector.

The system used to cool the detector readout hybrids is a custom implementation using closed freon and water circuits. It is designed to remove energy dissipated by the helix hybrids in the barrel (300 W) and wheels (120 W). The cooling system is controlled and read out through a programmable logic device (PLD), whose serial peripheral interface (SPI) bus is interfaced via a NIKHEF SPICAN [32] module to CANbus. The PLD continuously monitors environmental (pressure, temperature, humidity, airflow, etc.) parameters associated with the cooling system, and switches off the cooling if an error threshold is exceeded. Cold water, $\sim$11.5 ^∘C, is piped to the detector and distributed via a manifold to ladder and wheel cooling pipes; warm water is returned to the cooling system input. The entire system is flushed continuously with dry air in order to avoid condensation. A detailed description of the system including pictures can be found in [33].

NTC sensors are used to monitor 18 beampipe and 72 hybrid mounted sensors. The system’s SPI bus is interfaced via a NIKHEF SPICAN module to CANbus. The temperature readout system shares the cooling system’s CANbus. During data taking the barrel and wheel hybrid temperatures are typically 18 and 27 ^∘C, respectively.

The safety interlocks used are designed to ensure that the MVD low and bias voltages are off during injection or if a hardware failure occurs. In the off state no power from the MVD slow control system is dissipated in the detector. A Frenzel+Berg Easy-30 SPS/CAN  [34], connected by a separate CANbus, switches off the power to the hybrid low and bias voltage crates if one of the 4 bi-metal relays ($\sim$60^∘) mounted on the MVD support opens or if the cooling is off.

Slow control signals are additionally connected to the experiment’s interlock control which prevents beam injection if the MVD is on. Additional signals disable the trigger if the slow control is not in the configured state. Note that the experiment’s interlock system has no CANbus interface and the open/close (alarm/no alarm) signals are driven by logic connected to CST-DI8-TTL and CST-DO8-TTL input/output drivers  [35] connected to a separate CANbus. If the 5 second duty cycle clock driven from the CST control software stops then injection and triggers are disabled.

The slow control system reuses the hub based software developed for the run control system. Each sub-system control task has associated with it a hub public name, which allows new configuration messages to be sent and monitoring information to be received.

Configuration messages can be sent from scripts, a ROOT GUI, and via the Slow Control Control (SCC) system. SCC acts as a scheduler for slow control operations performed on more than one sub-system. During operation the cooling system remains on and the detector is switched between ON (voltages set) and STANDBY (zero volts) states by SCC. Additionally, the SCC drives the interlock levels such that when the detector is not in STANDBY injection is disabled, and when the detector is neither ON nor in STANDBY the trigger is disabled.

Monitoring information is made available via html query requests for tabulated statistics derived from messages held in the hub, or from histograms showing long term evolution of parameter values. This information and additional logfile data are archived.

The two most radiation sensitive components of the MVD are the Si sensors and the CMOS-based readout chips mounted inside the MVD volume. The sensitivity of the sensors has been tested using hadronic (reactor neutron irradiations) and ionising radiation ( ⁶⁰Co photon irradiation) [37].

After the neutron irradiation with up to $\phi_{eq}^{\mathrm{max}}=1\cdot 10^{13}~n_{eq}$ cm^-2 (much higher than the hadronic background expected during the MVD lifetime) no type inversion showed up as expected. After 3 weeks of annealing the leakage current had reached a value $420\,{\rm\mu A}$. After the ⁶⁰Co irradiation the leakage current reached 425 $\upmu$A which reduced to $140\,\upmu$A after 25 days of annealing. Testbeam measurements showed no change in performance of the sensors in terms of resolution and reduction of S/N [10].

As discussed earlier, the readout is based on the custom designed CMOS chip HELIX128-3.2 [15] designed in the AMS CYE 0.8 micron [14] process. One has therefore to expect changes of threshold voltages and transconductances of the MOS transistors for irradiations in the 1 kGy range. The design does not use any radiation tolerant layout techniques. On the other hand the setting of the transistors of the most sensitive parts of the design can be controlled by programmable DACs which can compensate the effects of irradiations to some extent.

For the irradiation of the Helix chips a test module was used consisting of only one sensor with the hybrid connected which carries the Helix chips The hybrid was tested in a separate ⁶⁰Co photon irradiation up to 5 kGy [38]. Figure 21 shows the S/N-ratio and the intrinsic position resolution as a function of the accumulated dose. The setting determining the bias current of the preamplifier is labelled $I_{pre}$ and the setting determining the feedback resistance of the shaper is labelled $V_{fs}$.

A deterioration of the performance after irradiation was observed, and the single track resolution for perpendicular incidence in a single diode worsens from $7.2\,\upmu\textrm{m}$ before irradiation to $12.2\,\upmu\textrm{m}$ after 5 kGy. By optimising the programmable readout parameters, the resolution after irradiation can be improved to $10.6\,\upmu\textrm{m}$. The resulting performance was thus still within the specified range [38].

In summary both sensitive parts of the MVD can survive a dose of more than 1 kGy before the performance deteriorates considerably. Since the MVD was foreseen to operate for five years at ZEUS a dose of more than 20 $\upmu$Gy/s could be safely allowed assuming a year of $10^{7}$ seconds duty time.

The radiation monitor consists of 16 Si pin diodes of $1\,{\rm cm^{2}}$ size [39] arranged in 8 pairs and mounted inside the MVD volume as shown in Figure 22. The two diodes of each pair are separated by $1\,\textrm{mm}$ of Pb to provide a discrimination between currents produced by mips and photons. Each pair of diodes is equipped with an NTC resistor to provide a temperature measurement for leakage current corrections. The diodes are connected via a $30\,$m doubly shielded cable to the data aquisition and HV supplies. Initially the diodes have been reverse-biased at $100\,$V. Later the voltage was reduced to $50\,$V (February 2005) to allow for more stable running conditions.

The current measured in the reverse-biased diodes consists of the rate of energy deposited in the diodes and of the leakage currents. Assuming an energy of $3.6\,$eV for the production of one electron-hole pair the dose rate and the current are related by

The deposition of energy in the diodes leads to radiation damage which results in an increase of the leakage current. At the time of writing the original leakage currents of below 1 nA have increased to about $200\,$nA at $50\,$V biasing for diodes on the inside of the ring.

The currents are fed into a two stage integrating amplifier whose voltages are measured by a commercial ADC with a resolution of $10\,$mV/nA. The range of the ADC reaches up to $10\,$V allowing a maximum current of $1000\,$nA corresponding to $50\,$mGy/s dose rate. The leakage currents are monitored regularly with no beams in the storage ring. The measured leakage currents, corrected for temperature, are the basis of the dose measurements. For the monitoring and the control of the dump signals the so called leaky-bucket concept developed by the BaBar experiment [40] is used. This concept allows a certain amount of excursions of the dose rate. The dump signal is released only after a certain deposited dose. Above a threshold of $0.5\,$Gy/s, the integration of the dose rate starts. A dump signal will be issued only if a dose of $200\,$mGy has been reached. To control the dose for rates below the threshold human intervention is needed.

Initially a software driven system with a $1\,$s sampling rate was used. In 2006 a new DAQ system was installed which reduces the reaction times from seconds to milliseconds thereby reducing the received doses before dumping.

In parallel to the current measurement two integrating systems have been installed at the beginning of the operation of the MVD: thermoluminescent dosimeters(TLD) and radiation field effect transistors (RadFet) [41]. The positions are indicated in Figure 22. Whereas the TLDs have to be exchanged regularly for reading, the RadFets can be read out continously by a remote data aquisition. Two types of TLDs have been used:

• •

  ⁷LiF (TLD-700) being sensitive to ionising radiation

• •

  and ⁶LiF (TLD-600) being sensitive to both ionising radiation and thermal neutrons by means of $(n,\alpha)$ capture.

In the shutdown in March 2003, 20 months after the beginning of the HERA II operation, all RadFets were exchanged. In addition another type of RadFet was installed at $Z=-60$ and $-110\,\textrm{cm}$ which can be read out continously [41]. The TLDs were not used after March 2003.

All dose rate and dose related measurements show a very non-uniform distribution. The highest values are found at the ring inside at negative $Z$, supporting simulations which predict a high rate of off-momentum leptons (Figure 23). The trigger rates of the ZEUS experiment show the same dependency. The total dose received at $Z=-130\,$cm for the ring inside position is approximately $2\,$kGy. The doses measured with the TLDs until 2003 are in general agreement with the RadFet measurements. The diodes at $Z=-60\,$cm and $Z=-110\,$cm which were installed later, received $1.5\,$kGy and $1.7\,$kGy respectively. During the same period the diodes at $Z=-130\,$cm received $0.75\,$kGy. Between the two positions $Z=-110$ and $-130\,$cm a scintillator-lead sandwich at $Z=-120\,$cm and vacuum flanges act as an extra collimator and can therefore explain the different dose values.

The performance of the MVD modules shows a similar tendency as the dose measurements: a small increase of noise for modules in cylinder 0 at the ring inside positions and negative $Z$-position (Figure 26) decreasing from negative $Z$ to positive $Z$ position leading to a decrease of S/N of up to $10\,$%. A total dose of close to $3\,$kGy as measured by the RadFets would have led to a decrease of the S/N of about $33\,$%. The difference can be understood by the fact that the Radfets are positioned as close as $25\,$mm to the beam whereas the readout electronics of cylinder 0/ladder 0 has a distance of close to $50\,$mm from the beam.

The offline track reconstruction beyond the local coordinate level consists of the track pattern recognition, the track fit, the vertex finding and the vertex fit. The track pattern recognition makes full use of the track finding powers of the individual detectors and proceeds through a complex multipass algorithm which combines CTD, forward and barrel MVD in a transparent way. This has the advantage that the track finding efficiency of the CTD is effectively enhanced by the MVD. Seeds are constructed from superlayers of both systems, and the resulting initial trajectories are then used to collect additional hits. In the MVD, also seeds consisting partly of barrel and partly of forward MVD hits are constructed to cover the transition area. Track candidates with ample hit information from both CTD and MVD take precedence, but also tracks composed entirely from MVD or CTD hits are found in later passes of the procedure, which extends the range beyond the CTD acceptance. The information assigned to a track then enters the track fit [42], which is based on the Kalman filter method. The track fit determines the accurate track parameters and their covariances taking the detailed material distribution of the MVD and the beampipe elements into account. Effects from both multiple scattering and ionization energy loss are accounted for. The track fit also rejects outlier hits based on their $\chi^{2}$ contribution to the fit. Also the vertex finder and vertex fit make use of the Kalman filter technique.

For the performance in highly resolution-dependent analyses, the quality of the detector alignment plays a crucial rôle. For this reason a four-step strategy was adopted. In the first step, during construction, both the position of half modules on the ladders and the position of the ladders inside the completed detector were surveyed with a precision of $10\,\,\upmu\textrm{m}$. For the second step a laser alignment system has been incorporated in the overall support structure to monitor the stability of the MVD in its operating environment. The primary aim of the system is to define periods of the stability for the more precise track-based alignment procedures. Those were performed using both cosmics and electron-proton collisions. In the following, the methods and results of the MVD alignment procedures are described in more detail.

The tracking efficiency is a quantity that depends not only on details of the detector but to a significant degree on details of hit and track reconstruction, such as clustering algorithms, track pattern recognition, the track fit, the alignment of the detector and many other parameters. Here we give only a simple estimation of this quantity which indicates that the tracking efficiency is indeed high. For this purpose Figure 36 shows the percentage of tracks found in the CTD that have either at least 2 or at least 4 associated hits in the MVD as a function of the azimutal angle.

This quantity approximately measures the MVD efficiency folded with that of the track pattern recognition. Impurity in the CTD hit selection causes a slight underestimate while impurity in the MVD cluster selection causes a slight overestimate. Overall the efficiency is flat at a level in excess of $98\,\%$ as a function of the polar angle with three characteristic dips near $0^{\circ}$, $80^{\circ}$ and $180^{\circ}$. These dips are due on the one hand to holes in the geometrical acceptance of the detector and to an accumulation of bad channels. In particular these are two small holes in the coverage of the inner cylinder near $0^{\circ}$ and $80^{\circ}$, the presence of only two cylinders near $180^{\circ}$ and an accumulation of bad channels around $80^{\circ}$.

The analog detector electronics provides a 10-bit value of the observed pulse height which is related to the specific energy loss of particles traversing the sensitive volume of the detector. These values calibrated to one for a pure sample of pions, e. g. from the decay of neutral kaons, are shown in Figure 37. One can easily identify the three different bands stemming from protons, kaons and pions. The resolution is around $11\,$% varying slightly with momentum and particle species.

The improved track reconstruction and accuracy of the MVD has enabled the experiment to use impact parameter and decay length signatures in heavy flavor analysis. One example is the reconstruction of the $D^{+}$ meson in its decay channel $D^{+}\rightarrow K^{-}\pi^{+}\pi^{+}$. The MVD allows detection of this decay pattern routinely as a displaced secondary vertex, as illustrated in the event display in Figure 38. For each accepted $D^{+}$ candidate, the decay length in the plane transverse to the beam, $l_{xy}$, has been calculated as

where $p_{x}$ and $p_{y}$ are the components of the transverse momentum of the $D^{+}$, $X_{vtx}$ and $Y_{vtx}$ are its vertex coordinates, and $X_{bsp}$ and $Y_{bsp}$ are the transverse coordinates of the beam spot. The decay length significance has been computed as $S_{l,xy}=l_{xy}/\sigma(l_{xy})$, where the error $\sigma(l_{xy})$ takes the resolutions of tracks and beam spot into account. Fig. 39 shows the resulting invariant mass spectrum for $S_{l,xy}>5$ and $p_{T}>3$ GeV, for DIS events collected in the $e^{-}p$ run between December 2004 and September 2005, corresponding to an integrated luminosity of $91~pb^{-1}$. The mass spectrum shows a very clean signal of $D^{+}$ mesons with very little background, thanks to the suppression of tracks from the primary interaction. The data sample has been used to determine the mean lifetime of the $D^{+}$ with an accurary of 10% [47] in agreement with the world average. This illustrates the flavor-tagging capabilities of the ZEUS Micro-Vertex Detector.