Using ZDDs in the Mapping of Quantum Circuits

Today’s NISQ-era quantum devices [10] support some given set of single- and two-qubit quantum gates. While single-qubit operations can be executed on any of the physical qubits, two-qubit quantum gates can only be performed by a pair of qubits that share a physical connection. The set of permissible qubit pairs are referred to as the coupling constraints. One task in quantum compilation algorithms is the mapping of a quantum circuit or algorithm, a sequence of quantum operations, onto the physical qubits of the device such that all two-qubit operations are executed with respect to device coupling constraints. This task is not always possible without including additional gates in the circuit.

Finding an optimum solution that minimizes the number of additional gates is “NP-hard” [3]. In order to efficiently find a solution, several heuristics have been proposed [12, 15, 6, 8]. Past work in mapping algorithms for quantum circuits are reported in [4, 13]. A common bottleneck in these heuristic methods is due to the large combinational search space resulting in numerous possible ways of mapping the gates to the device.

In this paper, we discuss how zero-suppressed decision diagrams (ZDDs, [9, 7]) can be used in mapping algorithms to combat combinational complexity. These data structures were selected because nearest neighbor couplings within quantum devices make the possible connections between qubits in a quantum circuit a sparse set, and ZDDs, as compared to other types of decision diagrams, are efficient at representing sparse sets. We show how to implement two specific problems which appear in several heuristics: (1) finding a maximal subcircuit partition that can be mapped without adding gates, and (2) how to determine and choose among all possible SWAP circuits that can execute in parallel in order to extend a partition. Once a maximal subcircuit partition is determined, a pseudo to physical qubit permutation from that partition is used to map the quantum circuit to a technology platform. If the maximal partition spans the entire quantum circuit, the result of ZDD mapping is a circuit that is fully mapped with respect to the coupling constraints of a device.

Finding maximal partitions for quantum circuit mapping is solved using SAT in [6]. In contrast to the SAT-based solution that finds one possible mapping, the ZDD-based algorithm generates all possible mappings for a maximal partition. All solutions are represented implicitly by means of a decision diagram, which may be used to count all solutions, query some solutions, or compute the solution that minimizes some linear cost function. All such tasks can be performed in time that is linear with respect to the size of the ZDD. All possible parallel SWAP operations used to extend the size of a partition are also stored in a ZDD.

The algorithms reported in this paper are intended to serve as motivating examples to illustrate how ZDDs may be used as a data structure for implementing a mapping algorithm. These algorithms have been prototyped and evaluated on a set of benchmarks. Effectiveness of the ZDD mapping algorithms is determined by using them in a preprocessing step for the publically-available compilers developed for the IBM and Rigetti quantum devices.

In this paper, we model the quantum circuit that is to be mapped to a quantum device as a set of pseudo qubits $V=\{v_{\lx@text@underscore}1,\dots,v_{\lx@text@underscore}n\}$ and an ordered sequence of two-qubit gates $G_{\lx@text@underscore}j=g_{\lx@text@underscore}1,\dots,g_{\lx@text@underscore}n$, with $g_{\lx@text@underscore}i\in\binom{V}{2}$. We can safely ignore the one-qubit gates in the circuit, since the coupling constraints of the device do not affect their mapping. Also note that we do not take the direction of a gate (e.g., the position of control and target in a $CX$) into account as unidirectional gates may be reversed, as seen in [12], with single qubit operations.

A quantum device is modeled by an undirected graph $(P,E)$, where $P=\{p_{\lx@text@underscore}1,\dots,p_{\lx@text@underscore}m\}$ is a set of physical qubits and an edge $\{p,q\}\in E\subseteq\binom{P}{2}$ states that a 2-qubit operation can be executed using the two physical qubits $p$ and $q$.

The goal is to find a mapping $\varphi:V\to P$ of pseudo qubits into physical ones, such that all two-qubit operations in the circuit are executed on adjacent qubits according to the device’s coupling constraints. It may not be possible to find such mapping for the input circuit. For example, there exists no such mapping for the example circuit, since the pseudo qubit $b$ interacts with three other qubits. However, by adding SWAP gates to reorder pseudo qubits, a mapping can be achieved. A SWAP gate is a two-qubit operation that can either be implemented with $CX$ or single-qubit rotations and $CZ$.

The aim is to use a small number of SWAP gates when transforming an initial circuit to a circuit that can be mapped into a target device. Finding the globally optimum mapping and a transformed circuit using the fewest number of SWAP gates is a computationally complex and time-consuming task [3].

To address the problem of finding maximal partitions for a circuit using ZDDs, we use partitions where

• •

  there exists a $(V,G_{\lx@text@underscore}j)$ that is a subgraph of $(P,E)$ for $1\leq j\leq l$,

• •

  there is not a $(V,G_{\lx@text@underscore}j\cup\{g_{\lx@text@underscore}{{e_{\lx@text@underscore}j+1}}\})$ that is a subgraph of $(P,E)$ for $1\leq j<l$.

Each partition has an associated set of mappings of pseudo to physical qubits $\Phi_{\lx@text@underscore}j=\{\varphi:V\mapsto P\}\$ where $\varphi$ is a subgraph isomorphism of $(V,G_{\lx@text@underscore}j)$ to $(P,E)$. If partition $G_{\lx@text@underscore}j$ starting at gate $g_{\lx@text@underscore}b$ cannot be extended, SWAP operations are inserted to merge the last gate of the partition, $g_{\lx@text@underscore}e$ with the adjacent gate, $g_{\lx@text@underscore}{e+1}$, in the circuit. These swapping operations, referred to as layers, exchange information on the adjacent physical qubits of the device and are executable in parallel within a single time cycle. The best SWAP layer is chosen according to a scoring metric. Once selected, the SWAP layer merges the gate $g_{\lx@text@underscore}{i}$ with $g_{\lx@text@underscore}{i+1}$ by inserting SWAP gates before $g_{\lx@text@underscore}{i+1}$, extending $G_{\lx@text@underscore}j$.

Ideally, a single partition will cover the entire circuit, providing a set of mappings that assign pseudo qubits to physical qubits on the device. In the case that multiple partitions exist that are fully extended with inserted SWAP layers, a mapping for the circuit is selected using the largest, and therefore maximal, partition.

In this section, we describe how to use ZDDs and ZDD operations to find a maximal partition that starts in some gate $g_{\lx@text@underscore}i$. The ZDDs are defined over the $nm$ variables $vp$ for each $v\in V$ and each $p\in P$. Each ZDD represents a family of finite subsets, and each subset $\alpha$ represents a partial mapping $\varphi:V\to P$, where $\varphi(v)=p$, if and only if $vp\in\alpha$ where $\alpha$ is a mapping.

First, we define some general sets, which are used throughout the following operations. It is sufficient to initialize these sets once at the beginning of the algorithm. The set

contains all singleton mappings $v\mapsto p$ for some $v\in V$. Analogously, the set

contains all singleton mappings $v\mapsto p$ for some $p\in P$.

Using this set, we can define two other helpful sets, valid and bad, using the ZDD family algebra operations. The set valid contains all two-element partial mappings that are feasible with respect to the coupling constraints of the device:

The set bad contains all two element sets of illegal partial mappings, because they either contain an element with two images or two elements which map to the same image:

Last, we define the set $\textit{map}(i)$ which represents all possible mappings of the pseudo qubits in gate $g_{\lx@text@underscore}i=\{v,w\}$:

In other words, we first join all possible mappings of $v$ with all possible mappings of $w$, before we restrict the result two-element subsets to those which are valid with respect to the target device.

Finally, the possible mappings of two consecutive gates $g_{\lx@text@underscore}i$ and $g_{\lx@text@underscore}{i+1}$ can be computed using

In some instances, Eqn. 7 results in the empty set, $\emptyset$, whenever the mappings of two consecutive gates are combined. In this case, SWAP procedures must be performed on physical qubits to exchange pseudo qubit information and extend the partition $G_{\lx@text@underscore}j$.

Finding an ideal SWAP circuit during quantum circuit mapping is an intractable problem that works in an exponentially-growing state space. In our method, we narrow this search space by focusing on the implementation of all SWAP circuits that can be executed in parallel during a single time cycle. We call this particular set of SWAP circuits layers, and it is a combination set rather than permutation set of ordered SWAP operations. ZDDs are a good data structure for combinatorial set representation, so a ZDD is implemented to represent the layers set. Acceptable SWAP operations are determined by the topology of the device, and the sets of operations that can be executed simultaneously within a time cycle are desired. ZDDs are used to create a set of all “good” SWAP circuits, which are those that interact with at least one qubit in the image of $\varphi$ and the depth of the circuit is one, i.e., a SWAP circuit may only contain multiple SWAP gates as long as qubits between gates are not shared. The ZDDs for this task differ from those used to enumerate all mappings, and they do not share any variables. The SWAP circuit ZDDs are defined over the $|E|$ variables $e$ for each $e\in E$ since SWAP gates can only be placed on certain edges connecting physical qubits according to the quantum device operational characteristics. We initialize the ZDD base, or the 1-terminal node, with the following ZDD. For each $p\in P$, the ZDD

contains all SWAPs that interact with qubit $p$.

All possible subsets of SWAP gates that can be executed in parallel (i.e., in depth 1) are described by the ZDD

Not all combinations of SWAP gates in layers may be useful for extending a partition of gates. For example, some SWAP circuits may allow the partition $G_{\lx@text@underscore}j$ to extend further and have greater depth while others provide more mapping options within $\Phi_{\lx@text@underscore}j$. As a result, a scoring function is calculated for each member of layers to determine the optimal SWAP decision every time it is desired to extend a circuit partition. The function of

Algorithm 1 implements ZDD data structures and the aforementioned ZDD operations to compute maximal partitions of quantum circuits starting from the first gate. A counter $j$ indicates the current partition number as the algorithm parses through the operators in the network. In $m$, a set of mappings are stored and updated as the current partition increases in size. These maps are eventually stored in $\Phi_{\lx@text@underscore}j$. For each gate $i$ we try to extend $m$ by adding the gate using $\textit{map}(i)$, and storing the resulting mappings in $m^{\prime}$. If $m^{\prime}$ is empty, $layers$ will be used to determine if a SWAP operation can be implemented in order to increase the current partition. The $scores$ for all of the sets in $layers$ are calculated, and the SWAP circuit with the largest $score$ is used to extend the partition. After the SWAP is implemented, the topology of the device is updated, maximum $score$ $m^{\prime}$ is calculated, and $m$ is updated with $m^{\prime}$. If the maximum $score$ is zero, then the then the current partition ends at $i-1$, and a new partition $j+1$ starts at gate $i$.

The algorithm discussed in the previous section implements the mapping of pseudo qubits in a quantum circuit specification to physical qubits on a real device. While the mapping procedure is essential for for quantum compilation, additional optimization steps can further improve the technology-mapped logic. For this reason, we propose the incorporation of the ZDD mapping techniques into a larger logic synthesis flow. In this procedure, mapping would occur after a circuit has been decomposed into one- and two-qubit operators and before a specification is compiled by a device’s custom compilation tool. Completing synthesis with available compilation tools allows the opportunity to take advantage of existing optimization algorithms while the operators of the circuit are transformed into a platform’s native gate library. Additionally, if the maximal partition found by the ZDD mapper does not cover the entire circuit, the native compiler of the technology platform is required to ensure that the placement of the two-qubit operators does not violate the coupling constraints of the device. It should be noted that although the ZDD mapping algorithm was evaluated using superconducting qubits as a target platform, the techniques described here are applicable to other quantum technologies that have coupling restrictions.

The ZDD quantum mapping algorithm was developed in C++ and was incorporated in the tweedledum logic synthesis library found in reference [11]. A subset of benchmarks from [2] were selected to evaluate the methods described in this work. These benchmarks contain a variety of reversible arithmetic and quantum algorithms such as a Grover’s algorithm oracle, a demonstration of the Quantum Fourier Transform (QFT), and various Toffoli implementations. The benchmark set was chosen for experimentation because they are functions commonly seen in quantum synthisis literature and are publicly available for use. These benchmarks are originally specified in a .qc file format with a gate set that contains physically unrealizable multi-qubit gates. Thus, the specifications are transformed into the Clifford+T library of single- and two-qubit gates using the “phasefold” pass of the Feynman toolkit [2] . After this procedure, the benchmarks are in a technology-independent form that consists of elementary gates. Mapping to a target quantum device may now begin.

A ring topology was chosen as the target device during synthesis. A ring structure was chosen because this type of architecture is seen in commercial QPUs like in Rigetti’s Agave and Aspen quantum machines. Additionally, the benefit of this structure is that it allows for a homogeneous testing environment that is flexible in size while using benchmarks that vary in number of pseudo qubits. Each benchmark was targeted to a device that contained $n$ physical qubits where $n$ is the number of pseudo qubits in a quantum algorithm. In these devices, all qubits are connected to their two adjacent neighbors, as seen in Fig. 2(b), and the connections are bidirectional with respect to the placement of the two-qubit $CX$ gate. Once the circuit and topology are selected, Algorithm 1 is applied to map the pseudo qubits in the design to physical qubits. The scoring operation of Eqn. 10 that chooses between the SWAP circuits in $layers$ to extend the partition is set to zero, one, and one for the depth, map, and SWAP weights, respectively. If the benchmark can be covered by an entire partition during the application of Algorithm 1, then the resulting specification is in a fully technology-mapped form and therefore compatible with the available connections of the target device. If multiple partitions are needed for a benchmark, the resulting specification is mapped using a permutation of the largest partition, making additional SWAP operations required for the design to be fully compatible with the target technology. This additional circuit modification is accomplished by the custom compilers that are provided with the Rigetti and IBM SDKs. Compiling the ZDD mapped circuits into the selected device topology with the available Rigetti and IBM compilers is the final procedure in the mapping flow. This step also ensures that all algorithm operations are translated into gates appropriate for the target device. Note that such a translation cannot lead to any further violations of the coupling constraints. After the final compilation step, the circuits are ready for execution on their respective platform since they are in a technology-mapped and optimized form. Details about the benchmarks along with experimental results of the mapping and compilation procedures can be found in Table 1.

In Table 1, details about gate depth, gate volume, and two-qubit gate count have been included for the ZDD mapped and compiled circuits. Metrics for the benchmarks after transformation with just the ZDD mapping procedures are also shown for reference. It should be noted that circuits transformed with only the ZDD mapper can include additional SWAP circuitry to expand the mapping partitions, and only if the maximal partition covers the entire benchmark is the resulting circuit fully mapped for the target technology. Because it is often the case that multiple partitions cover a benchmark and the maximum partition must be chosen for pseudo to physical qubit mapping, transformation by the native compiler is required. This synthesis procedure also confirms that the benchmark circuits use the appropriate gate library for the targeted technology. The benchmarks were compiled with and without preprocessing the circuit with the ZDD mapper. Circuits that improved in metrics for a particular device and benchmark whenever ZDD mapping was implemented are emphasized. On average, benchmarks mapped to a Rigetti ring topology saw a decrease of around 10% with respect to gate depth, gate volume, and two-qubit gate count whenever ZDD mapping was included in technology-dependent logic synthesis flow before compilation. The IBM-compiled circuits, however, only saw an average decrease of 2.3% in gate depth, gate volume, and two-qubit gate count whenever ZDD mapping was used. Individual improvements in circuit metrics of up to approximately a 50% decrease was seen in gate volume on the Rigetti devices and up to approximately a 44% decrease was seen in depth on the IBM devices. These findings demonstrate the potential that ZDD mapping techniques have with respect to finding more optimal solutions whenever generating technology-dependent forms of quantum circuits.

We present a method for mapping quantum logic circuits to actual devices using ZDDs. The required operations and algorithm are described, and the implementation is developed and tested in a quantum compilation flow that targets devices meant for the Rigetti and IBM families of superconducting quantum computers. When experimental results are evaluated, it is observed that incorporating ZDD mapping into quantum logic synthesis in many cases allowed for more optimal circuits to be found in their technology-dependent form. These results suggest that the ZDD may be a useful tool for quantum compilation that should be continued to be investigated in the future.